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Rev Log message Author Age Path
161 New directory structure. root 5588d 20h /can/tags/rel_20/bench/
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7351d 00h /can/tags/rel_20/bench/
140 I forgot to thange one signal name. igorm 7405d 22h /can/tags/rel_20/bench/
139 Signal bus_off_on added. igorm 7405d 23h /can/tags/rel_20/bench/
130 mbist signals updated according to newest convention markom 7559d 10h /can/tags/rel_20/bench/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7575d 19h /can/tags/rel_20/bench/
119 Artisan RAMs added. mohor 7617d 06h /can/tags/rel_20/bench/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7681d 01h /can/tags/rel_20/bench/
68 CAN inturrupt is active low. mohor 7764d 04h /can/tags/rel_20/bench/
63 ALE changes on negedge of clk. mohor 7775d 20h /can/tags/rel_20/bench/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7778d 10h /can/tags/rel_20/bench/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7778d 11h /can/tags/rel_20/bench/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7778d 11h /can/tags/rel_20/bench/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7785d 00h /can/tags/rel_20/bench/
50 Top level signal names changed. mohor 7785d 01h /can/tags/rel_20/bench/
48 Actel APA ram supported. mohor 7788d 17h /can/tags/rel_20/bench/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7799d 01h /can/tags/rel_20/bench/
38 Temporary backup version (still fully operable). mohor 7800d 15h /can/tags/rel_20/bench/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7800d 16h /can/tags/rel_20/bench/
35 Several registers added. Not finished, yet. mohor 7803d 20h /can/tags/rel_20/bench/
34 Errors monitoring improved. arbitration_lost improved. mohor 7806d 01h /can/tags/rel_20/bench/
31 Wishbone interface added. mohor 7807d 15h /can/tags/rel_20/bench/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7808d 21h /can/tags/rel_20/bench/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7809d 13h /can/tags/rel_20/bench/
26 Backup. mohor 7813d 22h /can/tags/rel_20/bench/
25 *** empty log message *** mohor 7814d 01h /can/tags/rel_20/bench/
24 backup. mohor 7818d 15h /can/tags/rel_20/bench/
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7833d 02h /can/tags/rel_20/bench/
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7833d 19h /can/tags/rel_20/bench/
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7834d 01h /can/tags/rel_20/bench/

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