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Rev Log message Author Age Path
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7464d 02h /can/tags/rel_24/
137 Header changed. mohor 7464d 03h /can/tags/rel_24/
136 Error counters changed. mohor 7464d 03h /can/tags/rel_24/
135 Header changed. mohor 7464d 03h /can/tags/rel_24/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7572d 00h /can/tags/rel_24/
130 mbist signals updated according to newest convention markom 7578d 11h /can/tags/rel_24/
129 Error counters changed. mohor 7594d 20h /can/tags/rel_24/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7594d 20h /can/tags/rel_24/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7595d 16h /can/tags/rel_24/
125 Synchronization changed, error counters fixed. mohor 7599d 22h /can/tags/rel_24/
124 ALTERA_RAM supported. mohor 7620d 04h /can/tags/rel_24/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7627d 10h /can/tags/rel_24/
119 Artisan RAMs added. mohor 7636d 07h /can/tags/rel_24/
118 Artisan RAM fixed (when not using BIST). mohor 7636d 07h /can/tags/rel_24/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7636d 07h /can/tags/rel_24/
115 Artisan ram instances added. simons 7642d 01h /can/tags/rel_24/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7669d 02h /can/tags/rel_24/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7671d 02h /can/tags/rel_24/
110 Fixed according to the linter. mohor 7671d 02h /can/tags/rel_24/
109 Fixed according to the linter. mohor 7671d 03h /can/tags/rel_24/
108 Fixed according to the linter. mohor 7671d 03h /can/tags/rel_24/
107 Fixed according to the linter. mohor 7671d 04h /can/tags/rel_24/
106 Unused signal removed. mohor 7677d 02h /can/tags/rel_24/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7677d 15h /can/tags/rel_24/
102 Little fixes (to fix warnings). mohor 7680d 06h /can/tags/rel_24/
100 Synchronization changed. mohor 7684d 08h /can/tags/rel_24/
99 PCI_BIST replaced with CAN_BIST. mohor 7684d 08h /can/tags/rel_24/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7689d 19h /can/tags/rel_24/
95 Virtual silicon ram instances added. simons 7689d 20h /can/tags/rel_24/
93 synthesis full_case parallel_case fixed. mohor 7695d 07h /can/tags/rel_24/

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