| Rev |
Log message |
Author |
Age |
Path |
| 56 |
Doubled declarations removed. |
mohor |
7799d 03h |
/can/tags/rel_6/rtl/verilog/ |
| 55 |
wire declaration added. |
mohor |
7799d 04h |
/can/tags/rel_6/rtl/verilog/ |
| 52 |
tx_o is now tristated signal. tx_oen and tx_o combined together. |
mohor |
7804d 05h |
/can/tags/rel_6/rtl/verilog/ |
| 51 |
Xilinx RAM added. |
mohor |
7804d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 50 |
Top level signal names changed. |
mohor |
7804d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 48 |
Actel APA ram supported. |
mohor |
7807d 22h |
/can/tags/rel_6/rtl/verilog/ |
| 47 |
Data is latched on read. |
mohor |
7807d 22h |
/can/tags/rel_6/rtl/verilog/ |
| 45 |
When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed. |
mohor |
7817d 20h |
/can/tags/rel_6/rtl/verilog/ |
| 44 |
When bit error occured while active error flag was transmitted, counter was
not incremented. |
mohor |
7817d 22h |
/can/tags/rel_6/rtl/verilog/ |
| 41 |
Incomplete sensitivity list fixed. |
mohor |
7818d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 40 |
Typo fixed. |
mohor |
7818d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 39 |
CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished. |
mohor |
7818d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 36 |
Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added. |
mohor |
7819d 21h |
/can/tags/rel_6/rtl/verilog/ |
| 35 |
Several registers added. Not finished, yet. |
mohor |
7823d 01h |
/can/tags/rel_6/rtl/verilog/ |
| 33 |
abort_tx added. |
mohor |
7825d 07h |
/can/tags/rel_6/rtl/verilog/ |
| 32 |
abort_tx added. Bit destuff fixed. |
mohor |
7825d 07h |
/can/tags/rel_6/rtl/verilog/ |
| 31 |
Wishbone interface added. |
mohor |
7826d 20h |
/can/tags/rel_6/rtl/verilog/ |
| 30 |
CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added. |
mohor |
7827d 05h |
/can/tags/rel_6/rtl/verilog/ |
| 29 |
Overload fixed. Hard synchronization also enabled at the last bit of
interframe. |
mohor |
7828d 02h |
/can/tags/rel_6/rtl/verilog/ |
| 28 |
Bosch license warning added. Error counters finished. Overload frames
still need to be fixed. |
mohor |
7828d 19h |
/can/tags/rel_6/rtl/verilog/ |
| 27 |
This file is not used. |
mohor |
7833d 03h |
/can/tags/rel_6/rtl/verilog/ |
| 26 |
Backup. |
mohor |
7833d 04h |
/can/tags/rel_6/rtl/verilog/ |
| 25 |
*** empty log message *** |
mohor |
7833d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 24 |
backup. |
mohor |
7837d 20h |
/can/tags/rel_6/rtl/verilog/ |
| 23 |
Fifo corrected to be synthesizable. |
mohor |
7851d 03h |
/can/tags/rel_6/rtl/verilog/ |
| 22 |
Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57). |
mohor |
7852d 07h |
/can/tags/rel_6/rtl/verilog/ |
| 21 |
Data is stored to fifo at the end of ack stage. |
mohor |
7852d 23h |
/can/tags/rel_6/rtl/verilog/ |
| 20 |
CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). |
mohor |
7853d 00h |
/can/tags/rel_6/rtl/verilog/ |
| 19 |
RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. |
mohor |
7853d 06h |
/can/tags/rel_6/rtl/verilog/ |
| 18 |
When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. |
mohor |
7853d 08h |
/can/tags/rel_6/rtl/verilog/ |
