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[/] [can/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5591d 19h /can/tags/rel_7/rtl/verilog/
94 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7679d 05h /can/tags/rel_7/rtl/verilog/
93 synthesis full_case parallel_case fixed. mohor 7679d 05h /can/tags/rel_7/rtl/verilog/
92 clkout is clk/2 after the reset. mohor 7679d 13h /can/tags/rel_7/rtl/verilog/
90 paralel_case and full_case compiler directives added to case statements. mohor 7680d 03h /can/tags/rel_7/rtl/verilog/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7681d 00h /can/tags/rel_7/rtl/verilog/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7681d 00h /can/tags/rel_7/rtl/verilog/
85 Typo fixed. mohor 7682d 16h /can/tags/rel_7/rtl/verilog/
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7683d 23h /can/tags/rel_7/rtl/verilog/
82 Removed few signals. mohor 7684d 00h /can/tags/rel_7/rtl/verilog/
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7684d 00h /can/tags/rel_7/rtl/verilog/
80 Form error was detected when stuff bit occured at the end of crc. mohor 7684d 00h /can/tags/rel_7/rtl/verilog/
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7685d 00h /can/tags/rel_7/rtl/verilog/
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7685d 01h /can/tags/rel_7/rtl/verilog/
77 Synchronization is also needed when transmitting a message. mohor 7688d 00h /can/tags/rel_7/rtl/verilog/
76 Counters width changed. mohor 7688d 00h /can/tags/rel_7/rtl/verilog/
75 When switching to tx, sync stage is overjumped. mohor 7690d 00h /can/tags/rel_7/rtl/verilog/
73 overrun and length_info fifos are initialized at the end of reset. mohor 7690d 05h /can/tags/rel_7/rtl/verilog/
71 Ports added for the CAN_BIST. mohor 7692d 03h /can/tags/rel_7/rtl/verilog/
70 data_out is already registered in the can_top.v file. mohor 7692d 03h /can/tags/rel_7/rtl/verilog/
69 Some features are supported in extended mode only (listen_only_mode...). mohor 7746d 23h /can/tags/rel_7/rtl/verilog/
67 CAN interrupt is active low. mohor 7767d 03h /can/tags/rel_7/rtl/verilog/
66 unix. mohor 7772d 22h /can/tags/rel_7/rtl/verilog/
65 unix. mohor 7772d 22h /can/tags/rel_7/rtl/verilog/
64 *** empty log message *** mohor 7772d 22h /can/tags/rel_7/rtl/verilog/
62 can_cs signal used for generation of the cs. mohor 7778d 19h /can/tags/rel_7/rtl/verilog/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7781d 09h /can/tags/rel_7/rtl/verilog/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7781d 10h /can/tags/rel_7/rtl/verilog/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7781d 11h /can/tags/rel_7/rtl/verilog/
58 timescale.v is used for simulation only. mohor 7781d 22h /can/tags/rel_7/rtl/verilog/

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