| Rev |
Log message |
Author |
Age |
Path |
| 44 |
When bit error occured while active error flag was transmitted, counter was
not incremented. |
mohor |
7802d 01h |
/can/tags/rel_7/rtl/verilog/ |
| 41 |
Incomplete sensitivity list fixed. |
mohor |
7802d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 40 |
Typo fixed. |
mohor |
7802d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 39 |
CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished. |
mohor |
7802d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 36 |
Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added. |
mohor |
7804d 01h |
/can/tags/rel_7/rtl/verilog/ |
| 35 |
Several registers added. Not finished, yet. |
mohor |
7807d 04h |
/can/tags/rel_7/rtl/verilog/ |
| 33 |
abort_tx added. |
mohor |
7809d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 32 |
abort_tx added. Bit destuff fixed. |
mohor |
7809d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 31 |
Wishbone interface added. |
mohor |
7811d 00h |
/can/tags/rel_7/rtl/verilog/ |
| 30 |
CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added. |
mohor |
7811d 09h |
/can/tags/rel_7/rtl/verilog/ |
| 29 |
Overload fixed. Hard synchronization also enabled at the last bit of
interframe. |
mohor |
7812d 06h |
/can/tags/rel_7/rtl/verilog/ |
| 28 |
Bosch license warning added. Error counters finished. Overload frames
still need to be fixed. |
mohor |
7812d 22h |
/can/tags/rel_7/rtl/verilog/ |
| 27 |
This file is not used. |
mohor |
7817d 07h |
/can/tags/rel_7/rtl/verilog/ |
| 26 |
Backup. |
mohor |
7817d 07h |
/can/tags/rel_7/rtl/verilog/ |
| 25 |
*** empty log message *** |
mohor |
7817d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 24 |
backup. |
mohor |
7821d 23h |
/can/tags/rel_7/rtl/verilog/ |
| 23 |
Fifo corrected to be synthesizable. |
mohor |
7835d 07h |
/can/tags/rel_7/rtl/verilog/ |
| 22 |
Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57). |
mohor |
7836d 11h |
/can/tags/rel_7/rtl/verilog/ |
| 21 |
Data is stored to fifo at the end of ack stage. |
mohor |
7837d 03h |
/can/tags/rel_7/rtl/verilog/ |
| 20 |
CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). |
mohor |
7837d 04h |
/can/tags/rel_7/rtl/verilog/ |
| 19 |
RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. |
mohor |
7837d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 18 |
When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. |
mohor |
7837d 11h |
/can/tags/rel_7/rtl/verilog/ |
| 17 |
Addresses corrected to decimal values (previously hex). |
mohor |
7838d 07h |
/can/tags/rel_7/rtl/verilog/ |
| 16 |
rx_fifo is now working. |
mohor |
7838d 12h |
/can/tags/rel_7/rtl/verilog/ |
| 15 |
Temporary version (backup). |
mohor |
7842d 07h |
/can/tags/rel_7/rtl/verilog/ |
| 14 |
rx fifo added. Not 100 % verified, yet. |
mohor |
7843d 03h |
/can/tags/rel_7/rtl/verilog/ |
| 13 |
Temporary files (backup). |
mohor |
7843d 10h |
/can/tags/rel_7/rtl/verilog/ |
| 12 |
Temp version. |
mohor |
7844d 11h |
/can/tags/rel_7/rtl/verilog/ |
| 11 |
Acceptance filter added. |
mohor |
7844d 22h |
/can/tags/rel_7/rtl/verilog/ |
| 10 |
Backup version. |
mohor |
7855d 20h |
/can/tags/rel_7/rtl/verilog/ |
