Rev |
Log message |
Author |
Age |
Path |
60 |
rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher. |
mohor |
7799d 08h |
/can/tags/rel_7/rtl/verilog/ |
59 |
8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file. |
mohor |
7799d 08h |
/can/tags/rel_7/rtl/verilog/ |
58 |
timescale.v is used for simulation only. |
mohor |
7799d 20h |
/can/tags/rel_7/rtl/verilog/ |
57 |
Mux used for clkout to avoid "gated clocks warning". |
mohor |
7799d 20h |
/can/tags/rel_7/rtl/verilog/ |
56 |
Doubled declarations removed. |
mohor |
7800d 19h |
/can/tags/rel_7/rtl/verilog/ |
55 |
wire declaration added. |
mohor |
7800d 19h |
/can/tags/rel_7/rtl/verilog/ |
52 |
tx_o is now tristated signal. tx_oen and tx_o combined together. |
mohor |
7805d 21h |
/can/tags/rel_7/rtl/verilog/ |
51 |
Xilinx RAM added. |
mohor |
7805d 21h |
/can/tags/rel_7/rtl/verilog/ |
50 |
Top level signal names changed. |
mohor |
7805d 21h |
/can/tags/rel_7/rtl/verilog/ |
48 |
Actel APA ram supported. |
mohor |
7809d 14h |
/can/tags/rel_7/rtl/verilog/ |
47 |
Data is latched on read. |
mohor |
7809d 14h |
/can/tags/rel_7/rtl/verilog/ |
45 |
When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed. |
mohor |
7819d 12h |
/can/tags/rel_7/rtl/verilog/ |
44 |
When bit error occured while active error flag was transmitted, counter was
not incremented. |
mohor |
7819d 13h |
/can/tags/rel_7/rtl/verilog/ |
41 |
Incomplete sensitivity list fixed. |
mohor |
7819d 21h |
/can/tags/rel_7/rtl/verilog/ |
40 |
Typo fixed. |
mohor |
7819d 21h |
/can/tags/rel_7/rtl/verilog/ |
39 |
CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished. |
mohor |
7819d 22h |
/can/tags/rel_7/rtl/verilog/ |
36 |
Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added. |
mohor |
7821d 12h |
/can/tags/rel_7/rtl/verilog/ |
35 |
Several registers added. Not finished, yet. |
mohor |
7824d 16h |
/can/tags/rel_7/rtl/verilog/ |
33 |
abort_tx added. |
mohor |
7826d 22h |
/can/tags/rel_7/rtl/verilog/ |
32 |
abort_tx added. Bit destuff fixed. |
mohor |
7826d 22h |
/can/tags/rel_7/rtl/verilog/ |
31 |
Wishbone interface added. |
mohor |
7828d 12h |
/can/tags/rel_7/rtl/verilog/ |
30 |
CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added. |
mohor |
7828d 20h |
/can/tags/rel_7/rtl/verilog/ |
29 |
Overload fixed. Hard synchronization also enabled at the last bit of
interframe. |
mohor |
7829d 18h |
/can/tags/rel_7/rtl/verilog/ |
28 |
Bosch license warning added. Error counters finished. Overload frames
still need to be fixed. |
mohor |
7830d 10h |
/can/tags/rel_7/rtl/verilog/ |
27 |
This file is not used. |
mohor |
7834d 19h |
/can/tags/rel_7/rtl/verilog/ |
26 |
Backup. |
mohor |
7834d 19h |
/can/tags/rel_7/rtl/verilog/ |
25 |
*** empty log message *** |
mohor |
7834d 22h |
/can/tags/rel_7/rtl/verilog/ |
24 |
backup. |
mohor |
7839d 11h |
/can/tags/rel_7/rtl/verilog/ |
23 |
Fifo corrected to be synthesizable. |
mohor |
7852d 19h |
/can/tags/rel_7/rtl/verilog/ |
22 |
Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57). |
mohor |
7853d 23h |
/can/tags/rel_7/rtl/verilog/ |