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[/] [can/] [trunk/] [bench/] [verilog/] - Rev 163

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Rev Log message Author Age Path
161 New directory structure. root 5629d 12h /can/trunk/bench/verilog/
160 New tests for testing the bus-off. igorm 6678d 18h /can/trunk/bench/verilog/
158 Fixing overrun problems. igorm 6966d 21h /can/trunk/bench/verilog/
140 I forgot to thange one signal name. igorm 7446d 14h /can/trunk/bench/verilog/
139 Signal bus_off_on added. igorm 7446d 14h /can/trunk/bench/verilog/
130 mbist signals updated according to newest convention markom 7600d 01h /can/trunk/bench/verilog/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7616d 10h /can/trunk/bench/verilog/
119 Artisan RAMs added. mohor 7657d 21h /can/trunk/bench/verilog/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7721d 16h /can/trunk/bench/verilog/
68 CAN inturrupt is active low. mohor 7804d 20h /can/trunk/bench/verilog/
63 ALE changes on negedge of clk. mohor 7816d 12h /can/trunk/bench/verilog/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7819d 01h /can/trunk/bench/verilog/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7819d 03h /can/trunk/bench/verilog/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7819d 03h /can/trunk/bench/verilog/
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7825d 16h /can/trunk/bench/verilog/
50 Top level signal names changed. mohor 7825d 16h /can/trunk/bench/verilog/
48 Actel APA ram supported. mohor 7829d 08h /can/trunk/bench/verilog/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7839d 16h /can/trunk/bench/verilog/
38 Temporary backup version (still fully operable). mohor 7841d 07h /can/trunk/bench/verilog/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7841d 07h /can/trunk/bench/verilog/
35 Several registers added. Not finished, yet. mohor 7844d 11h /can/trunk/bench/verilog/
34 Errors monitoring improved. arbitration_lost improved. mohor 7846d 17h /can/trunk/bench/verilog/
31 Wishbone interface added. mohor 7848d 06h /can/trunk/bench/verilog/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7849d 13h /can/trunk/bench/verilog/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7850d 05h /can/trunk/bench/verilog/
26 Backup. mohor 7854d 14h /can/trunk/bench/verilog/
25 *** empty log message *** mohor 7854d 17h /can/trunk/bench/verilog/
24 backup. mohor 7859d 06h /can/trunk/bench/verilog/
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7873d 18h /can/trunk/bench/verilog/
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7874d 10h /can/trunk/bench/verilog/

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