OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] - Rev 22

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
22 aligned I/O port numbers to real mega8 jsauermann 5200d 23h /cpu_lecture/
21 fixed bug in Sign bit computation for SUB and CP instructions jsauermann 5202d 18h /cpu_lecture/
20 readability of 95xx instructions improved jsauermann 5234d 14h /cpu_lecture/
19 another bug in the decoding of two-cycle instructions fixed jsauermann 5234d 15h /cpu_lecture/
18 fixed a bug that caused double execution of some 95xx instructions jsauermann 5237d 17h /cpu_lecture/
17 fixed missing carry flag for ROR instruction jsauermann 5241d 15h /cpu_lecture/
16 fixed missing RD_M signal for IN instruction jsauermann 5250d 17h /cpu_lecture/
15 fixed SP auto inc/dec problem jsauermann 5250d 18h /cpu_lecture/
14 fixed wrong Q_RSEL for LDD instruction jsauermann 5252d 15h /cpu_lecture/
13 fixed fault in LDD/STD decoding jsauermann 5253d 15h /cpu_lecture/
12 fixed bug in decoding of I/O address for SP jsauermann 5254d 15h /cpu_lecture/
11 fixed fault is BSET/BCLR instruction jsauermann 5256d 15h /cpu_lecture/
10 wait decoder fault fixed jsauermann 5256d 20h /cpu_lecture/
9 renamed 'main' to 'hello' in build commands jsauermann 5257d 16h /cpu_lecture/
8 picture quality slightly improved jsauermann 5257d 21h /cpu_lecture/
7 support multiple port sizes in make_mem jsauermann 5257d 22h /cpu_lecture/
6 support multiple port sizes in make_mem jsauermann 5257d 23h /cpu_lecture/
5 support multiple port sizes in make_mem jsauermann 5257d 23h /cpu_lecture/
4 initial check-in jsauermann 5261d 19h /cpu_lecture/
3 initial check-in jsauermann 5262d 00h /cpu_lecture/
2 initial check-in jsauermann 5262d 17h /cpu_lecture/
1 The project and the structure was created root 5262d 18h /cpu_lecture/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.