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[/] [csa/] [trunk/] [bench/] - Rev 51

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Rev	Log message	Author	Age	Path
51	remove the using to iverilog and veriwell	simon111	5508d 10h	/csa/trunk/bench/
49	group_decrypt module simulate success	simon111	5514d 22h	/csa/trunk/bench/
48	improve key_schedule module	simon111	5519d 22h	/csa/trunk/bench/
46	delete key_comupter module and testbench	simon111	5520d 08h	/csa/trunk/bench/
42	add group_decrypt module	simon111	5524d 06h	/csa/trunk/bench/
41	add three moudule ts_serial_out ts_sync key_cnt	simon111	5524d 19h	/csa/trunk/bench/
40	add timescale.v file and fix a bug in key_schedule module	simon111	5524d 23h	/csa/trunk/bench/
37	improve write_data systemcall,	simon111	5526d 02h	/csa/trunk/bench/
36	improve read_date vpi sytemcall, add offset and size argument	simon111	5526d 04h	/csa/trunk/bench/
35	csa cli support binary test data	simon111	5526d 08h	/csa/trunk/bench/
29	fix some bugs	simon111	5527d 22h	/csa/trunk/bench/
27	improve makefiles	simon111	5528d 09h	/csa/trunk/bench/
24	New directory structure.	root	5564d 15h	/csa/trunk/bench/
23	testing key_schedule module	simon111	5647d 22h	/trunk/bench/
22	decrypt module testbench update	simon111	5687d 22h	/trunk/bench/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5701d 21h	/trunk/bench/
18	try to add decrypt module (not finished yet)	simon111	5711d 23h	/trunk/bench/
17	finish block_decypher module	simon111	5763d 04h	/trunk/bench/
15	finished key_schedule module	simon111	5770d 22h	/trunk/bench/
14	* empty log message *	simon111	5771d 22h	/trunk/bench/
13	add key_schedule module(note: this module is not right yet)	simon111	5771d 22h	/trunk/bench/
12	* empty log message *	simon111	5771d 23h	/trunk/bench/
9	add the pli module and bench for key_perm module	simon111	5805d 00h	/trunk/bench/
5	This commit was generated by cvs2svn to compensate for changes in r4, which included commits to RCS files with non-trunk default branches.	Simon111	6113d 20h	/trunk/bench/

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[/] [csa/] [trunk/] [bench/] - Rev 51

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