OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 139

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 New release of the debug interface (3rd. release). igorm 7404d 10h /dbg_interface/tags/asyst_2/
138 Temp version before changing dbg interface. igorm 7410d 14h /dbg_interface/tags/asyst_2/
136 Table describing chain codes added. igorm 7414d 15h /dbg_interface/tags/asyst_2/
135 'hz changed to 1'hz because Icarus complains. igorm 7417d 14h /dbg_interface/tags/asyst_2/
132 Documentation updated. Many missing things added. igorm 7418d 13h /dbg_interface/tags/asyst_2/
131 Documentation updated. Many missing things added. igorm 7418d 13h /dbg_interface/tags/asyst_2/
129 New documentation. mohor 7460d 12h /dbg_interface/tags/asyst_2/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7462d 20h /dbg_interface/tags/asyst_2/
126 run_sim.scr renamed to run_sim for VATS. mohor 7465d 19h /dbg_interface/tags/asyst_2/
124 Display for VATS added. mohor 7467d 16h /dbg_interface/tags/asyst_2/
123 All flipflops are reset. mohor 7467d 16h /dbg_interface/tags/asyst_2/
121 Port signals are all set to zero after reset. mohor 7470d 16h /dbg_interface/tags/asyst_2/
120 test stall_test added. mohor 7470d 19h /dbg_interface/tags/asyst_2/
119 cpu_stall_o activated as soon as bp occurs. mohor 7470d 20h /dbg_interface/tags/asyst_2/
117 Define name changed. mohor 7472d 16h /dbg_interface/tags/asyst_2/
116 Data latching changed when testing WB. mohor 7472d 16h /dbg_interface/tags/asyst_2/
115 More debug data added. mohor 7472d 20h /dbg_interface/tags/asyst_2/
114 CRC generation iand verification in bench changed. mohor 7472d 21h /dbg_interface/tags/asyst_2/
113 IDCODE test improved. mohor 7472d 22h /dbg_interface/tags/asyst_2/
112 dbg_tb_defines.v not used. mohor 7473d 17h /dbg_interface/tags/asyst_2/
111 Define tap_defines.v added to test bench. mohor 7473d 17h /dbg_interface/tags/asyst_2/
110 Waiting for "ready" improved. mohor 7473d 18h /dbg_interface/tags/asyst_2/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7473d 23h /dbg_interface/tags/asyst_2/
106 Sensitivity list updated. simons 7474d 21h /dbg_interface/tags/asyst_2/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7475d 12h /dbg_interface/tags/asyst_2/
102 New version. mohor 7475d 12h /dbg_interface/tags/asyst_2/
101 Almost finished. mohor 7475d 13h /dbg_interface/tags/asyst_2/
100 *** empty log message *** mohor 7476d 15h /dbg_interface/tags/asyst_2/
99 cpu registers added. mohor 7476d 15h /dbg_interface/tags/asyst_2/
97 Working. mohor 7477d 18h /dbg_interface/tags/asyst_2/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.