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[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 144

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Rev Log message Author Age Path
144 Port names and defines for the supported CPUs changed. igorm 7391d 18h /dbg_interface/tags/asyst_2/
143 Signals for easier debugging removed. igorm 7391d 20h /dbg_interface/tags/asyst_2/
142 Typo fixed. igorm 7391d 21h /dbg_interface/tags/asyst_2/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7392d 16h /dbg_interface/tags/asyst_2/
140 CRC checking of incoming CRC added to all tasks. igorm 7393d 07h /dbg_interface/tags/asyst_2/
139 New release of the debug interface (3rd. release). igorm 7395d 10h /dbg_interface/tags/asyst_2/
138 Temp version before changing dbg interface. igorm 7401d 13h /dbg_interface/tags/asyst_2/
136 Table describing chain codes added. igorm 7405d 15h /dbg_interface/tags/asyst_2/
135 'hz changed to 1'hz because Icarus complains. igorm 7408d 14h /dbg_interface/tags/asyst_2/
132 Documentation updated. Many missing things added. igorm 7409d 13h /dbg_interface/tags/asyst_2/
131 Documentation updated. Many missing things added. igorm 7409d 13h /dbg_interface/tags/asyst_2/
129 New documentation. mohor 7451d 12h /dbg_interface/tags/asyst_2/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7453d 20h /dbg_interface/tags/asyst_2/
126 run_sim.scr renamed to run_sim for VATS. mohor 7456d 19h /dbg_interface/tags/asyst_2/
124 Display for VATS added. mohor 7458d 16h /dbg_interface/tags/asyst_2/
123 All flipflops are reset. mohor 7458d 16h /dbg_interface/tags/asyst_2/
121 Port signals are all set to zero after reset. mohor 7461d 16h /dbg_interface/tags/asyst_2/
120 test stall_test added. mohor 7461d 19h /dbg_interface/tags/asyst_2/
119 cpu_stall_o activated as soon as bp occurs. mohor 7461d 20h /dbg_interface/tags/asyst_2/
117 Define name changed. mohor 7463d 16h /dbg_interface/tags/asyst_2/
116 Data latching changed when testing WB. mohor 7463d 16h /dbg_interface/tags/asyst_2/
115 More debug data added. mohor 7463d 20h /dbg_interface/tags/asyst_2/
114 CRC generation iand verification in bench changed. mohor 7463d 21h /dbg_interface/tags/asyst_2/
113 IDCODE test improved. mohor 7463d 22h /dbg_interface/tags/asyst_2/
112 dbg_tb_defines.v not used. mohor 7464d 17h /dbg_interface/tags/asyst_2/
111 Define tap_defines.v added to test bench. mohor 7464d 17h /dbg_interface/tags/asyst_2/
110 Waiting for "ready" improved. mohor 7464d 17h /dbg_interface/tags/asyst_2/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7464d 23h /dbg_interface/tags/asyst_2/
106 Sensitivity list updated. simons 7465d 21h /dbg_interface/tags/asyst_2/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7466d 11h /dbg_interface/tags/asyst_2/

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