OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 150

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
150 Zero is shifted out when CTRL_READ command is active. igorm 7393d 11h /dbg_interface/tags/asyst_2/
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7395d 17h /dbg_interface/tags/asyst_2/
146 Changes for the FormalPRO. igorm 7399d 13h /dbg_interface/tags/asyst_2/
145 Support for 2 CPUs added. igorm 7399d 18h /dbg_interface/tags/asyst_2/
144 Port names and defines for the supported CPUs changed. igorm 7399d 19h /dbg_interface/tags/asyst_2/
143 Signals for easier debugging removed. igorm 7399d 20h /dbg_interface/tags/asyst_2/
142 Typo fixed. igorm 7399d 21h /dbg_interface/tags/asyst_2/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7400d 16h /dbg_interface/tags/asyst_2/
140 CRC checking of incoming CRC added to all tasks. igorm 7401d 07h /dbg_interface/tags/asyst_2/
139 New release of the debug interface (3rd. release). igorm 7403d 10h /dbg_interface/tags/asyst_2/
138 Temp version before changing dbg interface. igorm 7409d 14h /dbg_interface/tags/asyst_2/
136 Table describing chain codes added. igorm 7413d 15h /dbg_interface/tags/asyst_2/
135 'hz changed to 1'hz because Icarus complains. igorm 7416d 14h /dbg_interface/tags/asyst_2/
132 Documentation updated. Many missing things added. igorm 7417d 13h /dbg_interface/tags/asyst_2/
131 Documentation updated. Many missing things added. igorm 7417d 14h /dbg_interface/tags/asyst_2/
129 New documentation. mohor 7459d 12h /dbg_interface/tags/asyst_2/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7461d 20h /dbg_interface/tags/asyst_2/
126 run_sim.scr renamed to run_sim for VATS. mohor 7464d 20h /dbg_interface/tags/asyst_2/
124 Display for VATS added. mohor 7466d 16h /dbg_interface/tags/asyst_2/
123 All flipflops are reset. mohor 7466d 16h /dbg_interface/tags/asyst_2/
121 Port signals are all set to zero after reset. mohor 7469d 17h /dbg_interface/tags/asyst_2/
120 test stall_test added. mohor 7469d 19h /dbg_interface/tags/asyst_2/
119 cpu_stall_o activated as soon as bp occurs. mohor 7469d 20h /dbg_interface/tags/asyst_2/
117 Define name changed. mohor 7471d 16h /dbg_interface/tags/asyst_2/
116 Data latching changed when testing WB. mohor 7471d 16h /dbg_interface/tags/asyst_2/
115 More debug data added. mohor 7471d 20h /dbg_interface/tags/asyst_2/
114 CRC generation iand verification in bench changed. mohor 7471d 21h /dbg_interface/tags/asyst_2/
113 IDCODE test improved. mohor 7471d 22h /dbg_interface/tags/asyst_2/
112 dbg_tb_defines.v not used. mohor 7472d 17h /dbg_interface/tags/asyst_2/
111 Define tap_defines.v added to test bench. mohor 7472d 17h /dbg_interface/tags/asyst_2/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.