OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 93

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
93 tmp version. mohor 7501d 11h /dbg_interface/tags/asyst_2/
92 temp version. mohor 7504d 15h /dbg_interface/tags/asyst_2/
91 tmp version. mohor 7505d 10h /dbg_interface/tags/asyst_2/
90 tmp version. mohor 7506d 05h /dbg_interface/tags/asyst_2/
89 temp4 version. mohor 7507d 10h /dbg_interface/tags/asyst_2/
88 temp3 version. mohor 7508d 05h /dbg_interface/tags/asyst_2/
87 tmp2 version. mohor 7509d 10h /dbg_interface/tags/asyst_2/
86 Tmp version. mohor 7522d 06h /dbg_interface/tags/asyst_2/
85 New directory structure. New debug interface. mohor 7522d 07h /dbg_interface/tags/asyst_2/
84 Removed files that are not needed any more. mohor 7522d 07h /dbg_interface/tags/asyst_2/
83 Small fix. mohor 7522d 07h /dbg_interface/tags/asyst_2/
82 New directory structure. New version of the debug interface. mohor 7522d 07h /dbg_interface/tags/asyst_2/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7522d 07h /dbg_interface/tags/asyst_2/
80 New version of the debug interface. Not finished, yet. mohor 7522d 08h /dbg_interface/tags/asyst_2/
77 MBIST chain connection fixed. mohor 7583d 04h /dbg_interface/tags/asyst_2/
75 Simulation files. mohor 7583d 06h /dbg_interface/tags/asyst_2/
74 Removed. mohor 7583d 06h /dbg_interface/tags/asyst_2/
73 CRC logic changed. mohor 7583d 06h /dbg_interface/tags/asyst_2/
71 Mbist support added. simons 7585d 13h /dbg_interface/tags/asyst_2/
70 A pdf copy of existing doc document. simons 7592d 14h /dbg_interface/tags/asyst_2/
69 WBCNTL added, multiple CPU support described. simons 7613d 04h /dbg_interface/tags/asyst_2/
67 Lower two address lines must be always zero. simons 7618d 08h /dbg_interface/tags/asyst_2/
65 WB_CNTL register added, some syncronization fixes. simons 7619d 08h /dbg_interface/tags/asyst_2/
63 Three more chains added for cpu debug access. simons 7639d 09h /dbg_interface/tags/asyst_2/
61 Lapsus fixed. simons 7667d 08h /dbg_interface/tags/asyst_2/
59 Reset value for riscsel register set to 1. simons 7667d 09h /dbg_interface/tags/asyst_2/
57 Multiple cpu support added. simons 7667d 10h /dbg_interface/tags/asyst_2/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7934d 06h /dbg_interface/tags/asyst_2/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7934d 07h /dbg_interface/tags/asyst_2/
53 Trst active high. Inverted on higher layer. mohor 7934d 08h /dbg_interface/tags/asyst_2/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.