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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 102

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Rev Log message Author Age Path
102 New version. mohor 7462d 03h /dbg_interface/tags/asyst_2/rtl/
101 Almost finished. mohor 7462d 04h /dbg_interface/tags/asyst_2/rtl/
100 *** empty log message *** mohor 7463d 06h /dbg_interface/tags/asyst_2/rtl/
99 cpu registers added. mohor 7463d 06h /dbg_interface/tags/asyst_2/rtl/
97 Working. mohor 7464d 09h /dbg_interface/tags/asyst_2/rtl/
95 Temp version. mohor 7464d 22h /dbg_interface/tags/asyst_2/rtl/
94 temp version. Resets will be changed in next version. mohor 7465d 08h /dbg_interface/tags/asyst_2/rtl/
93 tmp version. mohor 7466d 09h /dbg_interface/tags/asyst_2/rtl/
92 temp version. mohor 7469d 13h /dbg_interface/tags/asyst_2/rtl/
91 tmp version. mohor 7470d 08h /dbg_interface/tags/asyst_2/rtl/
90 tmp version. mohor 7471d 03h /dbg_interface/tags/asyst_2/rtl/
89 temp4 version. mohor 7472d 09h /dbg_interface/tags/asyst_2/rtl/
88 temp3 version. mohor 7473d 03h /dbg_interface/tags/asyst_2/rtl/
87 tmp2 version. mohor 7474d 08h /dbg_interface/tags/asyst_2/rtl/
86 Tmp version. mohor 7487d 04h /dbg_interface/tags/asyst_2/rtl/
83 Small fix. mohor 7487d 05h /dbg_interface/tags/asyst_2/rtl/
82 New directory structure. New version of the debug interface. mohor 7487d 06h /dbg_interface/tags/asyst_2/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7487d 06h /dbg_interface/tags/asyst_2/rtl/
77 MBIST chain connection fixed. mohor 7548d 03h /dbg_interface/tags/asyst_2/rtl/
73 CRC logic changed. mohor 7548d 04h /dbg_interface/tags/asyst_2/rtl/
71 Mbist support added. simons 7550d 11h /dbg_interface/tags/asyst_2/rtl/
67 Lower two address lines must be always zero. simons 7583d 07h /dbg_interface/tags/asyst_2/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7584d 06h /dbg_interface/tags/asyst_2/rtl/
63 Three more chains added for cpu debug access. simons 7604d 07h /dbg_interface/tags/asyst_2/rtl/
61 Lapsus fixed. simons 7632d 07h /dbg_interface/tags/asyst_2/rtl/
59 Reset value for riscsel register set to 1. simons 7632d 07h /dbg_interface/tags/asyst_2/rtl/
57 Multiple cpu support added. simons 7632d 08h /dbg_interface/tags/asyst_2/rtl/
53 Trst active high. Inverted on higher layer. mohor 7899d 06h /dbg_interface/tags/asyst_2/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7899d 06h /dbg_interface/tags/asyst_2/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7926d 18h /dbg_interface/tags/asyst_2/rtl/

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