OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Three more chains added for cpu debug access. simons 7624d 01h /dbg_interface/tags/asyst_2/rtl/
61 Lapsus fixed. simons 7652d 01h /dbg_interface/tags/asyst_2/rtl/
59 Reset value for riscsel register set to 1. simons 7652d 01h /dbg_interface/tags/asyst_2/rtl/
57 Multiple cpu support added. simons 7652d 03h /dbg_interface/tags/asyst_2/rtl/
53 Trst active high. Inverted on higher layer. mohor 7919d 01h /dbg_interface/tags/asyst_2/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7919d 01h /dbg_interface/tags/asyst_2/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7946d 12h /dbg_interface/tags/asyst_2/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8102d 00h /dbg_interface/tags/asyst_2/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8110d 06h /dbg_interface/tags/asyst_2/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8117d 02h /dbg_interface/tags/asyst_2/rtl/
44 Signal names changed to lower case. mohor 8117d 02h /dbg_interface/tags/asyst_2/rtl/
43 Intentional error removed. mohor 8122d 02h /dbg_interface/tags/asyst_2/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8122d 04h /dbg_interface/tags/asyst_2/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8130d 01h /dbg_interface/tags/asyst_2/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8144d 01h /dbg_interface/tags/asyst_2/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8145d 02h /dbg_interface/tags/asyst_2/rtl/
38 Few outputs for boundary scan chain added. mohor 8158d 01h /dbg_interface/tags/asyst_2/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8158d 05h /dbg_interface/tags/asyst_2/rtl/
36 Structure changed. Hooks for jtag chain added. mohor 8162d 00h /dbg_interface/tags/asyst_2/rtl/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8192d 03h /dbg_interface/tags/asyst_2/rtl/
32 Stupid bug that was entered by previous update fixed. mohor 8193d 01h /dbg_interface/tags/asyst_2/rtl/
31 trst synchronization is not needed and was removed. mohor 8193d 02h /dbg_interface/tags/asyst_2/rtl/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8204d 07h /dbg_interface/tags/asyst_2/rtl/
28 TDO and TDO Enable signal are separated into two signals. mohor 8240d 04h /dbg_interface/tags/asyst_2/rtl/
27 Warnings from synthesys tools fixed. mohor 8254d 05h /dbg_interface/tags/asyst_2/rtl/
26 Warnings from synthesys tools fixed. mohor 8254d 05h /dbg_interface/tags/asyst_2/rtl/
25 trst signal is synchronized to wb_clk_i. mohor 8255d 02h /dbg_interface/tags/asyst_2/rtl/
23 Trace disabled by default. mohor 8262d 05h /dbg_interface/tags/asyst_2/rtl/
22 Register length fixed. mohor 8262d 05h /dbg_interface/tags/asyst_2/rtl/
21 CRC is returned when chain selection data is transmitted. mohor 8263d 01h /dbg_interface/tags/asyst_2/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.