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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 89

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Rev Log message Author Age Path
89 temp4 version. mohor 7492d 01h /dbg_interface/tags/asyst_2/rtl/
88 temp3 version. mohor 7492d 20h /dbg_interface/tags/asyst_2/rtl/
87 tmp2 version. mohor 7494d 01h /dbg_interface/tags/asyst_2/rtl/
86 Tmp version. mohor 7506d 21h /dbg_interface/tags/asyst_2/rtl/
83 Small fix. mohor 7506d 22h /dbg_interface/tags/asyst_2/rtl/
82 New directory structure. New version of the debug interface. mohor 7506d 22h /dbg_interface/tags/asyst_2/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7506d 22h /dbg_interface/tags/asyst_2/rtl/
77 MBIST chain connection fixed. mohor 7567d 19h /dbg_interface/tags/asyst_2/rtl/
73 CRC logic changed. mohor 7567d 21h /dbg_interface/tags/asyst_2/rtl/
71 Mbist support added. simons 7570d 03h /dbg_interface/tags/asyst_2/rtl/
67 Lower two address lines must be always zero. simons 7602d 23h /dbg_interface/tags/asyst_2/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7603d 23h /dbg_interface/tags/asyst_2/rtl/
63 Three more chains added for cpu debug access. simons 7623d 23h /dbg_interface/tags/asyst_2/rtl/
61 Lapsus fixed. simons 7651d 23h /dbg_interface/tags/asyst_2/rtl/
59 Reset value for riscsel register set to 1. simons 7652d 00h /dbg_interface/tags/asyst_2/rtl/
57 Multiple cpu support added. simons 7652d 01h /dbg_interface/tags/asyst_2/rtl/
53 Trst active high. Inverted on higher layer. mohor 7918d 23h /dbg_interface/tags/asyst_2/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7918d 23h /dbg_interface/tags/asyst_2/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7946d 11h /dbg_interface/tags/asyst_2/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 22h /dbg_interface/tags/asyst_2/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8110d 05h /dbg_interface/tags/asyst_2/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8117d 00h /dbg_interface/tags/asyst_2/rtl/
44 Signal names changed to lower case. mohor 8117d 00h /dbg_interface/tags/asyst_2/rtl/
43 Intentional error removed. mohor 8122d 00h /dbg_interface/tags/asyst_2/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8122d 02h /dbg_interface/tags/asyst_2/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8129d 23h /dbg_interface/tags/asyst_2/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8143d 23h /dbg_interface/tags/asyst_2/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8145d 00h /dbg_interface/tags/asyst_2/rtl/
38 Few outputs for boundary scan chain added. mohor 8157d 23h /dbg_interface/tags/asyst_2/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8158d 03h /dbg_interface/tags/asyst_2/rtl/

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