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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7469d 06h /dbg_interface/tags/highland_ver1/bench/
120 test stall_test added. mohor 7469d 09h /dbg_interface/tags/highland_ver1/bench/
117 Define name changed. mohor 7471d 05h /dbg_interface/tags/highland_ver1/bench/
116 Data latching changed when testing WB. mohor 7471d 06h /dbg_interface/tags/highland_ver1/bench/
115 More debug data added. mohor 7471d 09h /dbg_interface/tags/highland_ver1/bench/
114 CRC generation iand verification in bench changed. mohor 7471d 11h /dbg_interface/tags/highland_ver1/bench/
113 IDCODE test improved. mohor 7471d 12h /dbg_interface/tags/highland_ver1/bench/
112 dbg_tb_defines.v not used. mohor 7472d 06h /dbg_interface/tags/highland_ver1/bench/
111 Define tap_defines.v added to test bench. mohor 7472d 07h /dbg_interface/tags/highland_ver1/bench/
110 Waiting for "ready" improved. mohor 7472d 07h /dbg_interface/tags/highland_ver1/bench/
102 New version. mohor 7474d 02h /dbg_interface/tags/highland_ver1/bench/
101 Almost finished. mohor 7474d 03h /dbg_interface/tags/highland_ver1/bench/
99 cpu registers added. mohor 7475d 05h /dbg_interface/tags/highland_ver1/bench/
96 Working. mohor 7476d 09h /dbg_interface/tags/highland_ver1/bench/
95 Temp version. mohor 7476d 21h /dbg_interface/tags/highland_ver1/bench/
93 tmp version. mohor 7478d 08h /dbg_interface/tags/highland_ver1/bench/
92 temp version. mohor 7481d 12h /dbg_interface/tags/highland_ver1/bench/
91 tmp version. mohor 7482d 07h /dbg_interface/tags/highland_ver1/bench/
90 tmp version. mohor 7483d 02h /dbg_interface/tags/highland_ver1/bench/
89 temp4 version. mohor 7484d 08h /dbg_interface/tags/highland_ver1/bench/
88 temp3 version. mohor 7485d 03h /dbg_interface/tags/highland_ver1/bench/
87 tmp2 version. mohor 7486d 08h /dbg_interface/tags/highland_ver1/bench/
80 New version of the debug interface. Not finished, yet. mohor 7499d 05h /dbg_interface/tags/highland_ver1/bench/
75 Simulation files. mohor 7560d 03h /dbg_interface/tags/highland_ver1/bench/
73 CRC logic changed. mohor 7560d 04h /dbg_interface/tags/highland_ver1/bench/
63 Three more chains added for cpu debug access. simons 7616d 06h /dbg_interface/tags/highland_ver1/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8094d 05h /dbg_interface/tags/highland_ver1/bench/
38 Few outputs for boundary scan chain added. mohor 8150d 05h /dbg_interface/tags/highland_ver1/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8154d 04h /dbg_interface/tags/highland_ver1/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8294d 08h /dbg_interface/tags/highland_ver1/bench/

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