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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] - Rev 81

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Rev	Log message	Author	Age	Path
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7511d 21h	/dbg_interface/tags/highland_ver1/rtl/
77	MBIST chain connection fixed.	mohor	7572d 18h	/dbg_interface/tags/highland_ver1/rtl/
73	CRC logic changed.	mohor	7572d 20h	/dbg_interface/tags/highland_ver1/rtl/
71	Mbist support added.	simons	7575d 02h	/dbg_interface/tags/highland_ver1/rtl/
67	Lower two address lines must be always zero.	simons	7607d 22h	/dbg_interface/tags/highland_ver1/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7608d 22h	/dbg_interface/tags/highland_ver1/rtl/
63	Three more chains added for cpu debug access.	simons	7628d 22h	/dbg_interface/tags/highland_ver1/rtl/
61	Lapsus fixed.	simons	7656d 22h	/dbg_interface/tags/highland_ver1/rtl/
59	Reset value for riscsel register set to 1.	simons	7656d 23h	/dbg_interface/tags/highland_ver1/rtl/
57	Multiple cpu support added.	simons	7657d 00h	/dbg_interface/tags/highland_ver1/rtl/
53	Trst active high. Inverted on higher layer.	mohor	7923d 22h	/dbg_interface/tags/highland_ver1/rtl/
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7923d 22h	/dbg_interface/tags/highland_ver1/rtl/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7951d 10h	/dbg_interface/tags/highland_ver1/rtl/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8106d 22h	/dbg_interface/tags/highland_ver1/rtl/
46	Asynchronous reset used instead of synchronous.	mohor	8115d 04h	/dbg_interface/tags/highland_ver1/rtl/
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8121d 23h	/dbg_interface/tags/highland_ver1/rtl/
44	Signal names changed to lower case.	mohor	8121d 23h	/dbg_interface/tags/highland_ver1/rtl/
43	Intentional error removed.	mohor	8126d 23h	/dbg_interface/tags/highland_ver1/rtl/
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8127d 01h	/dbg_interface/tags/highland_ver1/rtl/
41	Function changed to logic because of some synthesis warnings.	mohor	8134d 22h	/dbg_interface/tags/highland_ver1/rtl/
40	Signal tdo_padoe_o changed back to tdo_padoen_o.	mohor	8148d 22h	/dbg_interface/tags/highland_ver1/rtl/
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8149d 23h	/dbg_interface/tags/highland_ver1/rtl/
38	Few outputs for boundary scan chain added.	mohor	8162d 22h	/dbg_interface/tags/highland_ver1/rtl/
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8163d 02h	/dbg_interface/tags/highland_ver1/rtl/
36	Structure changed. Hooks for jtag chain added.	mohor	8166d 21h	/dbg_interface/tags/highland_ver1/rtl/
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8197d 00h	/dbg_interface/tags/highland_ver1/rtl/
32	Stupid bug that was entered by previous update fixed.	mohor	8197d 23h	/dbg_interface/tags/highland_ver1/rtl/
31	trst synchronization is not needed and was removed.	mohor	8198d 00h	/dbg_interface/tags/highland_ver1/rtl/
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8209d 04h	/dbg_interface/tags/highland_ver1/rtl/
28	TDO and TDO Enable signal are separated into two signals.	mohor	8245d 01h	/dbg_interface/tags/highland_ver1/rtl/

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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] - Rev 81

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