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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5602d 02h /dbg_interface/tags/old_debug/rtl/verilog/
78 This commit was manufactured by cvs2svn to create tag 'old_debug'. 7567d 04h /dbg_interface/tags/old_debug/rtl/verilog/
77 MBIST chain connection fixed. mohor 7567d 04h /dbg_interface/tags/old_debug/rtl/verilog/
73 CRC logic changed. mohor 7567d 06h /dbg_interface/tags/old_debug/rtl/verilog/
71 Mbist support added. simons 7569d 12h /dbg_interface/tags/old_debug/rtl/verilog/
67 Lower two address lines must be always zero. simons 7602d 08h /dbg_interface/tags/old_debug/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7603d 08h /dbg_interface/tags/old_debug/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7623d 08h /dbg_interface/tags/old_debug/rtl/verilog/
61 Lapsus fixed. simons 7651d 08h /dbg_interface/tags/old_debug/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7651d 08h /dbg_interface/tags/old_debug/rtl/verilog/
57 Multiple cpu support added. simons 7651d 10h /dbg_interface/tags/old_debug/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7918d 08h /dbg_interface/tags/old_debug/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7918d 08h /dbg_interface/tags/old_debug/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7945d 19h /dbg_interface/tags/old_debug/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 07h /dbg_interface/tags/old_debug/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8109d 13h /dbg_interface/tags/old_debug/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8116d 09h /dbg_interface/tags/old_debug/rtl/verilog/
44 Signal names changed to lower case. mohor 8116d 09h /dbg_interface/tags/old_debug/rtl/verilog/
43 Intentional error removed. mohor 8121d 09h /dbg_interface/tags/old_debug/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8121d 11h /dbg_interface/tags/old_debug/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8129d 08h /dbg_interface/tags/old_debug/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8143d 08h /dbg_interface/tags/old_debug/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8144d 09h /dbg_interface/tags/old_debug/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8157d 08h /dbg_interface/tags/old_debug/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8157d 12h /dbg_interface/tags/old_debug/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8161d 07h /dbg_interface/tags/old_debug/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8191d 10h /dbg_interface/tags/old_debug/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8192d 09h /dbg_interface/tags/old_debug/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8192d 09h /dbg_interface/tags/old_debug/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8203d 14h /dbg_interface/tags/old_debug/rtl/verilog/

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