OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5562d 21h /dbg_interface/tags/rel_1/rtl/
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8062d 02h /dbg_interface/tags/rel_1/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8062d 02h /dbg_interface/tags/rel_1/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8070d 08h /dbg_interface/tags/rel_1/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8077d 04h /dbg_interface/tags/rel_1/rtl/
44 Signal names changed to lower case. mohor 8077d 04h /dbg_interface/tags/rel_1/rtl/
43 Intentional error removed. mohor 8082d 03h /dbg_interface/tags/rel_1/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8082d 05h /dbg_interface/tags/rel_1/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8090d 02h /dbg_interface/tags/rel_1/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8104d 02h /dbg_interface/tags/rel_1/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8105d 03h /dbg_interface/tags/rel_1/rtl/
38 Few outputs for boundary scan chain added. mohor 8118d 02h /dbg_interface/tags/rel_1/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8118d 06h /dbg_interface/tags/rel_1/rtl/
36 Structure changed. Hooks for jtag chain added. mohor 8122d 01h /dbg_interface/tags/rel_1/rtl/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8152d 04h /dbg_interface/tags/rel_1/rtl/
32 Stupid bug that was entered by previous update fixed. mohor 8153d 03h /dbg_interface/tags/rel_1/rtl/
31 trst synchronization is not needed and was removed. mohor 8153d 04h /dbg_interface/tags/rel_1/rtl/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8164d 09h /dbg_interface/tags/rel_1/rtl/
28 TDO and TDO Enable signal are separated into two signals. mohor 8200d 05h /dbg_interface/tags/rel_1/rtl/
27 Warnings from synthesys tools fixed. mohor 8214d 07h /dbg_interface/tags/rel_1/rtl/
26 Warnings from synthesys tools fixed. mohor 8214d 07h /dbg_interface/tags/rel_1/rtl/
25 trst signal is synchronized to wb_clk_i. mohor 8215d 03h /dbg_interface/tags/rel_1/rtl/
23 Trace disabled by default. mohor 8222d 07h /dbg_interface/tags/rel_1/rtl/
22 Register length fixed. mohor 8222d 07h /dbg_interface/tags/rel_1/rtl/
21 CRC is returned when chain selection data is transmitted. mohor 8223d 03h /dbg_interface/tags/rel_1/rtl/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8224d 06h /dbg_interface/tags/rel_1/rtl/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8236d 06h /dbg_interface/tags/rel_1/rtl/
18 Reset signals are not combined any more. mohor 8238d 15h /dbg_interface/tags/rel_1/rtl/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8262d 05h /dbg_interface/tags/rel_1/rtl/
15 bs_chain_o added. mohor 8264d 06h /dbg_interface/tags/rel_1/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.