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[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5581d 16h /dbg_interface/tags/rel_1/rtl/verilog/
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8080d 21h /dbg_interface/tags/rel_1/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8080d 21h /dbg_interface/tags/rel_1/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8089d 03h /dbg_interface/tags/rel_1/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8095d 23h /dbg_interface/tags/rel_1/rtl/verilog/
44 Signal names changed to lower case. mohor 8095d 23h /dbg_interface/tags/rel_1/rtl/verilog/
43 Intentional error removed. mohor 8100d 22h /dbg_interface/tags/rel_1/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8101d 00h /dbg_interface/tags/rel_1/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8108d 21h /dbg_interface/tags/rel_1/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8122d 21h /dbg_interface/tags/rel_1/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8123d 22h /dbg_interface/tags/rel_1/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8136d 21h /dbg_interface/tags/rel_1/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8137d 01h /dbg_interface/tags/rel_1/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8140d 20h /dbg_interface/tags/rel_1/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8170d 23h /dbg_interface/tags/rel_1/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8171d 22h /dbg_interface/tags/rel_1/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8171d 23h /dbg_interface/tags/rel_1/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8183d 04h /dbg_interface/tags/rel_1/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8219d 00h /dbg_interface/tags/rel_1/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8233d 01h /dbg_interface/tags/rel_1/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8233d 01h /dbg_interface/tags/rel_1/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8233d 22h /dbg_interface/tags/rel_1/rtl/verilog/
23 Trace disabled by default. mohor 8241d 02h /dbg_interface/tags/rel_1/rtl/verilog/
22 Register length fixed. mohor 8241d 02h /dbg_interface/tags/rel_1/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8241d 22h /dbg_interface/tags/rel_1/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8243d 01h /dbg_interface/tags/rel_1/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8255d 01h /dbg_interface/tags/rel_1/rtl/verilog/
18 Reset signals are not combined any more. mohor 8257d 10h /dbg_interface/tags/rel_1/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8281d 00h /dbg_interface/tags/rel_1/rtl/verilog/
15 bs_chain_o added. mohor 8283d 01h /dbg_interface/tags/rel_1/rtl/verilog/

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