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[/] [dbg_interface/] [tags/] [rel_12/] - Rev 96

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Rev Log message Author Age Path
96 Working. mohor 7472d 08h /dbg_interface/tags/rel_12/
95 Temp version. mohor 7472d 20h /dbg_interface/tags/rel_12/
94 temp version. Resets will be changed in next version. mohor 7473d 06h /dbg_interface/tags/rel_12/
93 tmp version. mohor 7474d 07h /dbg_interface/tags/rel_12/
92 temp version. mohor 7477d 11h /dbg_interface/tags/rel_12/
91 tmp version. mohor 7478d 06h /dbg_interface/tags/rel_12/
90 tmp version. mohor 7479d 01h /dbg_interface/tags/rel_12/
89 temp4 version. mohor 7480d 07h /dbg_interface/tags/rel_12/
88 temp3 version. mohor 7481d 02h /dbg_interface/tags/rel_12/
87 tmp2 version. mohor 7482d 07h /dbg_interface/tags/rel_12/
86 Tmp version. mohor 7495d 02h /dbg_interface/tags/rel_12/
85 New directory structure. New debug interface. mohor 7495d 03h /dbg_interface/tags/rel_12/
84 Removed files that are not needed any more. mohor 7495d 03h /dbg_interface/tags/rel_12/
83 Small fix. mohor 7495d 03h /dbg_interface/tags/rel_12/
82 New directory structure. New version of the debug interface. mohor 7495d 04h /dbg_interface/tags/rel_12/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7495d 04h /dbg_interface/tags/rel_12/
80 New version of the debug interface. Not finished, yet. mohor 7495d 04h /dbg_interface/tags/rel_12/
77 MBIST chain connection fixed. mohor 7556d 01h /dbg_interface/tags/rel_12/
75 Simulation files. mohor 7556d 02h /dbg_interface/tags/rel_12/
74 Removed. mohor 7556d 02h /dbg_interface/tags/rel_12/
73 CRC logic changed. mohor 7556d 03h /dbg_interface/tags/rel_12/
71 Mbist support added. simons 7558d 09h /dbg_interface/tags/rel_12/
70 A pdf copy of existing doc document. simons 7565d 11h /dbg_interface/tags/rel_12/
69 WBCNTL added, multiple CPU support described. simons 7586d 00h /dbg_interface/tags/rel_12/
67 Lower two address lines must be always zero. simons 7591d 05h /dbg_interface/tags/rel_12/
65 WB_CNTL register added, some syncronization fixes. simons 7592d 04h /dbg_interface/tags/rel_12/
63 Three more chains added for cpu debug access. simons 7612d 05h /dbg_interface/tags/rel_12/
61 Lapsus fixed. simons 7640d 05h /dbg_interface/tags/rel_12/
59 Reset value for riscsel register set to 1. simons 7640d 05h /dbg_interface/tags/rel_12/
57 Multiple cpu support added. simons 7640d 06h /dbg_interface/tags/rel_12/

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