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[/] [dbg_interface/] [tags/] [rel_15/] - Rev 88

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Rev Log message Author Age Path
88 temp3 version. mohor 7554d 00h /dbg_interface/tags/rel_15/
87 tmp2 version. mohor 7555d 05h /dbg_interface/tags/rel_15/
86 Tmp version. mohor 7568d 01h /dbg_interface/tags/rel_15/
85 New directory structure. New debug interface. mohor 7568d 01h /dbg_interface/tags/rel_15/
84 Removed files that are not needed any more. mohor 7568d 01h /dbg_interface/tags/rel_15/
83 Small fix. mohor 7568d 01h /dbg_interface/tags/rel_15/
82 New directory structure. New version of the debug interface. mohor 7568d 02h /dbg_interface/tags/rel_15/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7568d 02h /dbg_interface/tags/rel_15/
80 New version of the debug interface. Not finished, yet. mohor 7568d 02h /dbg_interface/tags/rel_15/
77 MBIST chain connection fixed. mohor 7628d 23h /dbg_interface/tags/rel_15/
75 Simulation files. mohor 7629d 00h /dbg_interface/tags/rel_15/
74 Removed. mohor 7629d 00h /dbg_interface/tags/rel_15/
73 CRC logic changed. mohor 7629d 01h /dbg_interface/tags/rel_15/
71 Mbist support added. simons 7631d 07h /dbg_interface/tags/rel_15/
70 A pdf copy of existing doc document. simons 7638d 09h /dbg_interface/tags/rel_15/
69 WBCNTL added, multiple CPU support described. simons 7658d 22h /dbg_interface/tags/rel_15/
67 Lower two address lines must be always zero. simons 7664d 03h /dbg_interface/tags/rel_15/
65 WB_CNTL register added, some syncronization fixes. simons 7665d 02h /dbg_interface/tags/rel_15/
63 Three more chains added for cpu debug access. simons 7685d 03h /dbg_interface/tags/rel_15/
61 Lapsus fixed. simons 7713d 03h /dbg_interface/tags/rel_15/
59 Reset value for riscsel register set to 1. simons 7713d 03h /dbg_interface/tags/rel_15/
57 Multiple cpu support added. simons 7713d 05h /dbg_interface/tags/rel_15/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7980d 01h /dbg_interface/tags/rel_15/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7980d 01h /dbg_interface/tags/rel_15/
53 Trst active high. Inverted on higher layer. mohor 7980d 02h /dbg_interface/tags/rel_15/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7980d 03h /dbg_interface/tags/rel_15/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8007d 14h /dbg_interface/tags/rel_15/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 8007d 15h /dbg_interface/tags/rel_15/
47 mon_cntl_o signals that controls monitor mux added. mohor 8163d 02h /dbg_interface/tags/rel_15/
46 Asynchronous reset used instead of synchronous. mohor 8171d 08h /dbg_interface/tags/rel_15/

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