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[/] [dbg_interface/] [tags/] [rel_15/] - Rev 90

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Rev Log message Author Age Path
90 tmp version. mohor 7589d 11h /dbg_interface/tags/rel_15/
89 temp4 version. mohor 7590d 17h /dbg_interface/tags/rel_15/
88 temp3 version. mohor 7591d 11h /dbg_interface/tags/rel_15/
87 tmp2 version. mohor 7592d 16h /dbg_interface/tags/rel_15/
86 Tmp version. mohor 7605d 12h /dbg_interface/tags/rel_15/
85 New directory structure. New debug interface. mohor 7605d 13h /dbg_interface/tags/rel_15/
84 Removed files that are not needed any more. mohor 7605d 13h /dbg_interface/tags/rel_15/
83 Small fix. mohor 7605d 13h /dbg_interface/tags/rel_15/
82 New directory structure. New version of the debug interface. mohor 7605d 13h /dbg_interface/tags/rel_15/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7605d 13h /dbg_interface/tags/rel_15/
80 New version of the debug interface. Not finished, yet. mohor 7605d 14h /dbg_interface/tags/rel_15/
77 MBIST chain connection fixed. mohor 7666d 10h /dbg_interface/tags/rel_15/
75 Simulation files. mohor 7666d 12h /dbg_interface/tags/rel_15/
74 Removed. mohor 7666d 12h /dbg_interface/tags/rel_15/
73 CRC logic changed. mohor 7666d 12h /dbg_interface/tags/rel_15/
71 Mbist support added. simons 7668d 19h /dbg_interface/tags/rel_15/
70 A pdf copy of existing doc document. simons 7675d 21h /dbg_interface/tags/rel_15/
69 WBCNTL added, multiple CPU support described. simons 7696d 10h /dbg_interface/tags/rel_15/
67 Lower two address lines must be always zero. simons 7701d 15h /dbg_interface/tags/rel_15/
65 WB_CNTL register added, some syncronization fixes. simons 7702d 14h /dbg_interface/tags/rel_15/
63 Three more chains added for cpu debug access. simons 7722d 15h /dbg_interface/tags/rel_15/
61 Lapsus fixed. simons 7750d 15h /dbg_interface/tags/rel_15/
59 Reset value for riscsel register set to 1. simons 7750d 15h /dbg_interface/tags/rel_15/
57 Multiple cpu support added. simons 7750d 16h /dbg_interface/tags/rel_15/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8017d 13h /dbg_interface/tags/rel_15/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 8017d 13h /dbg_interface/tags/rel_15/
53 Trst active high. Inverted on higher layer. mohor 8017d 14h /dbg_interface/tags/rel_15/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 8017d 14h /dbg_interface/tags/rel_15/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8045d 02h /dbg_interface/tags/rel_15/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 8045d 03h /dbg_interface/tags/rel_15/

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