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[/] [dbg_interface/] [tags/] [rel_15/] - Rev 94

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Rev Log message Author Age Path
94 temp version. Resets will be changed in next version. mohor 7483d 12h /dbg_interface/tags/rel_15/
93 tmp version. mohor 7484d 13h /dbg_interface/tags/rel_15/
92 temp version. mohor 7487d 17h /dbg_interface/tags/rel_15/
91 tmp version. mohor 7488d 12h /dbg_interface/tags/rel_15/
90 tmp version. mohor 7489d 07h /dbg_interface/tags/rel_15/
89 temp4 version. mohor 7490d 13h /dbg_interface/tags/rel_15/
88 temp3 version. mohor 7491d 08h /dbg_interface/tags/rel_15/
87 tmp2 version. mohor 7492d 13h /dbg_interface/tags/rel_15/
86 Tmp version. mohor 7505d 08h /dbg_interface/tags/rel_15/
85 New directory structure. New debug interface. mohor 7505d 09h /dbg_interface/tags/rel_15/
84 Removed files that are not needed any more. mohor 7505d 09h /dbg_interface/tags/rel_15/
83 Small fix. mohor 7505d 09h /dbg_interface/tags/rel_15/
82 New directory structure. New version of the debug interface. mohor 7505d 10h /dbg_interface/tags/rel_15/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7505d 10h /dbg_interface/tags/rel_15/
80 New version of the debug interface. Not finished, yet. mohor 7505d 10h /dbg_interface/tags/rel_15/
77 MBIST chain connection fixed. mohor 7566d 07h /dbg_interface/tags/rel_15/
75 Simulation files. mohor 7566d 08h /dbg_interface/tags/rel_15/
74 Removed. mohor 7566d 08h /dbg_interface/tags/rel_15/
73 CRC logic changed. mohor 7566d 09h /dbg_interface/tags/rel_15/
71 Mbist support added. simons 7568d 15h /dbg_interface/tags/rel_15/
70 A pdf copy of existing doc document. simons 7575d 17h /dbg_interface/tags/rel_15/
69 WBCNTL added, multiple CPU support described. simons 7596d 06h /dbg_interface/tags/rel_15/
67 Lower two address lines must be always zero. simons 7601d 11h /dbg_interface/tags/rel_15/
65 WB_CNTL register added, some syncronization fixes. simons 7602d 10h /dbg_interface/tags/rel_15/
63 Three more chains added for cpu debug access. simons 7622d 11h /dbg_interface/tags/rel_15/
61 Lapsus fixed. simons 7650d 11h /dbg_interface/tags/rel_15/
59 Reset value for riscsel register set to 1. simons 7650d 11h /dbg_interface/tags/rel_15/
57 Multiple cpu support added. simons 7650d 13h /dbg_interface/tags/rel_15/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7917d 09h /dbg_interface/tags/rel_15/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7917d 09h /dbg_interface/tags/rel_15/

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