OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5676d 22h /dbg_interface/tags/rel_15/bench/
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7554d 11h /dbg_interface/tags/rel_15/bench/
102 New version. mohor 7556d 00h /dbg_interface/tags/rel_15/bench/
101 Almost finished. mohor 7556d 01h /dbg_interface/tags/rel_15/bench/
99 cpu registers added. mohor 7557d 03h /dbg_interface/tags/rel_15/bench/
96 Working. mohor 7558d 07h /dbg_interface/tags/rel_15/bench/
95 Temp version. mohor 7558d 19h /dbg_interface/tags/rel_15/bench/
93 tmp version. mohor 7560d 07h /dbg_interface/tags/rel_15/bench/
92 temp version. mohor 7563d 10h /dbg_interface/tags/rel_15/bench/
91 tmp version. mohor 7564d 05h /dbg_interface/tags/rel_15/bench/
90 tmp version. mohor 7565d 00h /dbg_interface/tags/rel_15/bench/
89 temp4 version. mohor 7566d 06h /dbg_interface/tags/rel_15/bench/
88 temp3 version. mohor 7567d 01h /dbg_interface/tags/rel_15/bench/
87 tmp2 version. mohor 7568d 06h /dbg_interface/tags/rel_15/bench/
80 New version of the debug interface. Not finished, yet. mohor 7581d 04h /dbg_interface/tags/rel_15/bench/
75 Simulation files. mohor 7642d 02h /dbg_interface/tags/rel_15/bench/
73 CRC logic changed. mohor 7642d 02h /dbg_interface/tags/rel_15/bench/
63 Three more chains added for cpu debug access. simons 7698d 04h /dbg_interface/tags/rel_15/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8176d 03h /dbg_interface/tags/rel_15/bench/
38 Few outputs for boundary scan chain added. mohor 8232d 04h /dbg_interface/tags/rel_15/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8236d 03h /dbg_interface/tags/rel_15/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8376d 07h /dbg_interface/tags/rel_15/bench/
15 bs_chain_o added. mohor 8378d 08h /dbg_interface/tags/rel_15/bench/
13 Signal names changed to lowercase. mohor 8379d 08h /dbg_interface/tags/rel_15/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8380d 08h /dbg_interface/tags/rel_15/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8401d 04h /dbg_interface/tags/rel_15/bench/
9 Working version. Few bugs fixed, comments added. mohor 8405d 08h /dbg_interface/tags/rel_15/bench/
6 Minor changes for simulation. mohor 8406d 06h /dbg_interface/tags/rel_15/bench/
5 Trace fixed. Some registers changed, trace simplified. mohor 8407d 04h /dbg_interface/tags/rel_15/bench/
2 Initial official release. mohor 8412d 04h /dbg_interface/tags/rel_15/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.