OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] [verilog/] - Rev 109

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7475d 02h /dbg_interface/tags/rel_15/bench/verilog/
102 New version. mohor 7476d 16h /dbg_interface/tags/rel_15/bench/verilog/
101 Almost finished. mohor 7476d 17h /dbg_interface/tags/rel_15/bench/verilog/
99 cpu registers added. mohor 7477d 19h /dbg_interface/tags/rel_15/bench/verilog/
96 Working. mohor 7478d 23h /dbg_interface/tags/rel_15/bench/verilog/
95 Temp version. mohor 7479d 11h /dbg_interface/tags/rel_15/bench/verilog/
93 tmp version. mohor 7480d 23h /dbg_interface/tags/rel_15/bench/verilog/
92 temp version. mohor 7484d 02h /dbg_interface/tags/rel_15/bench/verilog/
91 tmp version. mohor 7484d 21h /dbg_interface/tags/rel_15/bench/verilog/
90 tmp version. mohor 7485d 16h /dbg_interface/tags/rel_15/bench/verilog/
89 temp4 version. mohor 7486d 22h /dbg_interface/tags/rel_15/bench/verilog/
88 temp3 version. mohor 7487d 17h /dbg_interface/tags/rel_15/bench/verilog/
87 tmp2 version. mohor 7488d 22h /dbg_interface/tags/rel_15/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7501d 20h /dbg_interface/tags/rel_15/bench/verilog/
75 Simulation files. mohor 7562d 17h /dbg_interface/tags/rel_15/bench/verilog/
73 CRC logic changed. mohor 7562d 18h /dbg_interface/tags/rel_15/bench/verilog/
63 Three more chains added for cpu debug access. simons 7618d 20h /dbg_interface/tags/rel_15/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8096d 19h /dbg_interface/tags/rel_15/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8152d 19h /dbg_interface/tags/rel_15/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8156d 19h /dbg_interface/tags/rel_15/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8296d 22h /dbg_interface/tags/rel_15/bench/verilog/
15 bs_chain_o added. mohor 8298d 23h /dbg_interface/tags/rel_15/bench/verilog/
13 Signal names changed to lowercase. mohor 8300d 00h /dbg_interface/tags/rel_15/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8301d 00h /dbg_interface/tags/rel_15/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8321d 20h /dbg_interface/tags/rel_15/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8326d 00h /dbg_interface/tags/rel_15/bench/verilog/
6 Minor changes for simulation. mohor 8326d 22h /dbg_interface/tags/rel_15/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8327d 20h /dbg_interface/tags/rel_15/bench/verilog/
2 Initial official release. mohor 8332d 20h /dbg_interface/tags/rel_15/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.