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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 87

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Rev Log message Author Age Path
87 tmp2 version. mohor 7516d 20h /dbg_interface/tags/rel_15/rtl/verilog/
86 Tmp version. mohor 7529d 16h /dbg_interface/tags/rel_15/rtl/verilog/
83 Small fix. mohor 7529d 17h /dbg_interface/tags/rel_15/rtl/verilog/
82 New directory structure. New version of the debug interface. mohor 7529d 17h /dbg_interface/tags/rel_15/rtl/verilog/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7529d 17h /dbg_interface/tags/rel_15/rtl/verilog/
77 MBIST chain connection fixed. mohor 7590d 14h /dbg_interface/tags/rel_15/rtl/verilog/
73 CRC logic changed. mohor 7590d 16h /dbg_interface/tags/rel_15/rtl/verilog/
71 Mbist support added. simons 7592d 23h /dbg_interface/tags/rel_15/rtl/verilog/
67 Lower two address lines must be always zero. simons 7625d 19h /dbg_interface/tags/rel_15/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7626d 18h /dbg_interface/tags/rel_15/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7646d 19h /dbg_interface/tags/rel_15/rtl/verilog/
61 Lapsus fixed. simons 7674d 19h /dbg_interface/tags/rel_15/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7674d 19h /dbg_interface/tags/rel_15/rtl/verilog/
57 Multiple cpu support added. simons 7674d 20h /dbg_interface/tags/rel_15/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7941d 18h /dbg_interface/tags/rel_15/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7941d 18h /dbg_interface/tags/rel_15/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7969d 06h /dbg_interface/tags/rel_15/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8124d 18h /dbg_interface/tags/rel_15/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8133d 00h /dbg_interface/tags/rel_15/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8139d 20h /dbg_interface/tags/rel_15/rtl/verilog/
44 Signal names changed to lower case. mohor 8139d 20h /dbg_interface/tags/rel_15/rtl/verilog/
43 Intentional error removed. mohor 8144d 19h /dbg_interface/tags/rel_15/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8144d 21h /dbg_interface/tags/rel_15/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8152d 18h /dbg_interface/tags/rel_15/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8166d 18h /dbg_interface/tags/rel_15/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8167d 19h /dbg_interface/tags/rel_15/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8180d 18h /dbg_interface/tags/rel_15/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8180d 22h /dbg_interface/tags/rel_15/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8184d 17h /dbg_interface/tags/rel_15/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8214d 20h /dbg_interface/tags/rel_15/rtl/verilog/

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