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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 97

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Rev Log message Author Age Path
97 Working. mohor 7471d 23h /dbg_interface/tags/rel_15/rtl/verilog/
95 Temp version. mohor 7472d 12h /dbg_interface/tags/rel_15/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7472d 23h /dbg_interface/tags/rel_15/rtl/verilog/
93 tmp version. mohor 7474d 00h /dbg_interface/tags/rel_15/rtl/verilog/
92 temp version. mohor 7477d 03h /dbg_interface/tags/rel_15/rtl/verilog/
91 tmp version. mohor 7477d 22h /dbg_interface/tags/rel_15/rtl/verilog/
90 tmp version. mohor 7478d 17h /dbg_interface/tags/rel_15/rtl/verilog/
89 temp4 version. mohor 7479d 23h /dbg_interface/tags/rel_15/rtl/verilog/
88 temp3 version. mohor 7480d 18h /dbg_interface/tags/rel_15/rtl/verilog/
87 tmp2 version. mohor 7481d 23h /dbg_interface/tags/rel_15/rtl/verilog/
86 Tmp version. mohor 7494d 19h /dbg_interface/tags/rel_15/rtl/verilog/
83 Small fix. mohor 7494d 20h /dbg_interface/tags/rel_15/rtl/verilog/
82 New directory structure. New version of the debug interface. mohor 7494d 20h /dbg_interface/tags/rel_15/rtl/verilog/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7494d 20h /dbg_interface/tags/rel_15/rtl/verilog/
77 MBIST chain connection fixed. mohor 7555d 17h /dbg_interface/tags/rel_15/rtl/verilog/
73 CRC logic changed. mohor 7555d 19h /dbg_interface/tags/rel_15/rtl/verilog/
71 Mbist support added. simons 7558d 01h /dbg_interface/tags/rel_15/rtl/verilog/
67 Lower two address lines must be always zero. simons 7590d 21h /dbg_interface/tags/rel_15/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7591d 21h /dbg_interface/tags/rel_15/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7611d 21h /dbg_interface/tags/rel_15/rtl/verilog/
61 Lapsus fixed. simons 7639d 21h /dbg_interface/tags/rel_15/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7639d 21h /dbg_interface/tags/rel_15/rtl/verilog/
57 Multiple cpu support added. simons 7639d 23h /dbg_interface/tags/rel_15/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7906d 21h /dbg_interface/tags/rel_15/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7906d 21h /dbg_interface/tags/rel_15/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7934d 08h /dbg_interface/tags/rel_15/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 20h /dbg_interface/tags/rel_15/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8098d 02h /dbg_interface/tags/rel_15/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8104d 22h /dbg_interface/tags/rel_15/rtl/verilog/
44 Signal names changed to lower case. mohor 8104d 22h /dbg_interface/tags/rel_15/rtl/verilog/

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