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[/] [dbg_interface/] [tags/] [rel_16/] [bench/] - Rev 158

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Rev Log message Author Age Path
158 root 5571d 20h /dbg_interface/tags/rel_16/bench/
118 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7448d 01h /dbg_interface/tags/rel_16/bench/
117 Define name changed. mohor 7448d 01h /dbg_interface/tags/rel_16/bench/
116 Data latching changed when testing WB. mohor 7448d 02h /dbg_interface/tags/rel_16/bench/
115 More debug data added. mohor 7448d 05h /dbg_interface/tags/rel_16/bench/
114 CRC generation iand verification in bench changed. mohor 7448d 06h /dbg_interface/tags/rel_16/bench/
113 IDCODE test improved. mohor 7448d 08h /dbg_interface/tags/rel_16/bench/
112 dbg_tb_defines.v not used. mohor 7449d 02h /dbg_interface/tags/rel_16/bench/
111 Define tap_defines.v added to test bench. mohor 7449d 02h /dbg_interface/tags/rel_16/bench/
110 Waiting for "ready" improved. mohor 7449d 03h /dbg_interface/tags/rel_16/bench/
102 New version. mohor 7450d 22h /dbg_interface/tags/rel_16/bench/
101 Almost finished. mohor 7450d 23h /dbg_interface/tags/rel_16/bench/
99 cpu registers added. mohor 7452d 01h /dbg_interface/tags/rel_16/bench/
96 Working. mohor 7453d 05h /dbg_interface/tags/rel_16/bench/
95 Temp version. mohor 7453d 17h /dbg_interface/tags/rel_16/bench/
93 tmp version. mohor 7455d 04h /dbg_interface/tags/rel_16/bench/
92 temp version. mohor 7458d 08h /dbg_interface/tags/rel_16/bench/
91 tmp version. mohor 7459d 03h /dbg_interface/tags/rel_16/bench/
90 tmp version. mohor 7459d 22h /dbg_interface/tags/rel_16/bench/
89 temp4 version. mohor 7461d 04h /dbg_interface/tags/rel_16/bench/
88 temp3 version. mohor 7461d 22h /dbg_interface/tags/rel_16/bench/
87 tmp2 version. mohor 7463d 03h /dbg_interface/tags/rel_16/bench/
80 New version of the debug interface. Not finished, yet. mohor 7476d 01h /dbg_interface/tags/rel_16/bench/
75 Simulation files. mohor 7536d 23h /dbg_interface/tags/rel_16/bench/
73 CRC logic changed. mohor 7536d 23h /dbg_interface/tags/rel_16/bench/
63 Three more chains added for cpu debug access. simons 7593d 02h /dbg_interface/tags/rel_16/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8071d 01h /dbg_interface/tags/rel_16/bench/
38 Few outputs for boundary scan chain added. mohor 8127d 01h /dbg_interface/tags/rel_16/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8131d 00h /dbg_interface/tags/rel_16/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8271d 04h /dbg_interface/tags/rel_16/bench/

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