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[/] [dbg_interface/] [tags/] [rel_19/] - Rev 69

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Rev Log message Author Age Path
69 WBCNTL added, multiple CPU support described. simons 7616d 00h /dbg_interface/tags/rel_19/
67 Lower two address lines must be always zero. simons 7621d 04h /dbg_interface/tags/rel_19/
65 WB_CNTL register added, some syncronization fixes. simons 7622d 04h /dbg_interface/tags/rel_19/
63 Three more chains added for cpu debug access. simons 7642d 04h /dbg_interface/tags/rel_19/
61 Lapsus fixed. simons 7670d 04h /dbg_interface/tags/rel_19/
59 Reset value for riscsel register set to 1. simons 7670d 05h /dbg_interface/tags/rel_19/
57 Multiple cpu support added. simons 7670d 06h /dbg_interface/tags/rel_19/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7937d 02h /dbg_interface/tags/rel_19/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7937d 02h /dbg_interface/tags/rel_19/
53 Trst active high. Inverted on higher layer. mohor 7937d 04h /dbg_interface/tags/rel_19/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7937d 04h /dbg_interface/tags/rel_19/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7964d 16h /dbg_interface/tags/rel_19/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7964d 16h /dbg_interface/tags/rel_19/
47 mon_cntl_o signals that controls monitor mux added. mohor 8120d 04h /dbg_interface/tags/rel_19/
46 Asynchronous reset used instead of synchronous. mohor 8128d 10h /dbg_interface/tags/rel_19/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8135d 05h /dbg_interface/tags/rel_19/
44 Signal names changed to lower case. mohor 8135d 05h /dbg_interface/tags/rel_19/
43 Intentional error removed. mohor 8140d 05h /dbg_interface/tags/rel_19/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8140d 07h /dbg_interface/tags/rel_19/
41 Function changed to logic because of some synthesis warnings. mohor 8148d 04h /dbg_interface/tags/rel_19/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8162d 04h /dbg_interface/tags/rel_19/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8163d 05h /dbg_interface/tags/rel_19/
38 Few outputs for boundary scan chain added. mohor 8176d 04h /dbg_interface/tags/rel_19/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8176d 08h /dbg_interface/tags/rel_19/
36 Structure changed. Hooks for jtag chain added. mohor 8180d 03h /dbg_interface/tags/rel_19/
35 Dbg support datasheet added to cvs. mohor 8204d 07h /dbg_interface/tags/rel_19/
34 Product brief added to cvs. mohor 8205d 01h /dbg_interface/tags/rel_19/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8210d 06h /dbg_interface/tags/rel_19/
32 Stupid bug that was entered by previous update fixed. mohor 8211d 05h /dbg_interface/tags/rel_19/
31 trst synchronization is not needed and was removed. mohor 8211d 06h /dbg_interface/tags/rel_19/

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