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[/] [dbg_interface/] [tags/] [rel_19/] - Rev 84

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Rev Log message Author Age Path
84 Removed files that are not needed any more. mohor 7531d 11h /dbg_interface/tags/rel_19/
83 Small fix. mohor 7531d 11h /dbg_interface/tags/rel_19/
82 New directory structure. New version of the debug interface. mohor 7531d 11h /dbg_interface/tags/rel_19/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7531d 11h /dbg_interface/tags/rel_19/
80 New version of the debug interface. Not finished, yet. mohor 7531d 12h /dbg_interface/tags/rel_19/
77 MBIST chain connection fixed. mohor 7592d 08h /dbg_interface/tags/rel_19/
75 Simulation files. mohor 7592d 10h /dbg_interface/tags/rel_19/
74 Removed. mohor 7592d 10h /dbg_interface/tags/rel_19/
73 CRC logic changed. mohor 7592d 10h /dbg_interface/tags/rel_19/
71 Mbist support added. simons 7594d 17h /dbg_interface/tags/rel_19/
70 A pdf copy of existing doc document. simons 7601d 18h /dbg_interface/tags/rel_19/
69 WBCNTL added, multiple CPU support described. simons 7622d 08h /dbg_interface/tags/rel_19/
67 Lower two address lines must be always zero. simons 7627d 12h /dbg_interface/tags/rel_19/
65 WB_CNTL register added, some syncronization fixes. simons 7628d 12h /dbg_interface/tags/rel_19/
63 Three more chains added for cpu debug access. simons 7648d 12h /dbg_interface/tags/rel_19/
61 Lapsus fixed. simons 7676d 12h /dbg_interface/tags/rel_19/
59 Reset value for riscsel register set to 1. simons 7676d 13h /dbg_interface/tags/rel_19/
57 Multiple cpu support added. simons 7676d 14h /dbg_interface/tags/rel_19/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7943d 10h /dbg_interface/tags/rel_19/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7943d 11h /dbg_interface/tags/rel_19/
53 Trst active high. Inverted on higher layer. mohor 7943d 12h /dbg_interface/tags/rel_19/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7943d 12h /dbg_interface/tags/rel_19/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7971d 00h /dbg_interface/tags/rel_19/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7971d 00h /dbg_interface/tags/rel_19/
47 mon_cntl_o signals that controls monitor mux added. mohor 8126d 12h /dbg_interface/tags/rel_19/
46 Asynchronous reset used instead of synchronous. mohor 8134d 18h /dbg_interface/tags/rel_19/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8141d 13h /dbg_interface/tags/rel_19/
44 Signal names changed to lower case. mohor 8141d 14h /dbg_interface/tags/rel_19/
43 Intentional error removed. mohor 8146d 13h /dbg_interface/tags/rel_19/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8146d 15h /dbg_interface/tags/rel_19/

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