OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 112

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
112 dbg_tb_defines.v not used. mohor 7507d 20h /dbg_interface/tags/rel_19/bench/
111 Define tap_defines.v added to test bench. mohor 7507d 20h /dbg_interface/tags/rel_19/bench/
110 Waiting for "ready" improved. mohor 7507d 21h /dbg_interface/tags/rel_19/bench/
102 New version. mohor 7509d 16h /dbg_interface/tags/rel_19/bench/
101 Almost finished. mohor 7509d 17h /dbg_interface/tags/rel_19/bench/
99 cpu registers added. mohor 7510d 19h /dbg_interface/tags/rel_19/bench/
96 Working. mohor 7511d 23h /dbg_interface/tags/rel_19/bench/
95 Temp version. mohor 7512d 11h /dbg_interface/tags/rel_19/bench/
93 tmp version. mohor 7513d 22h /dbg_interface/tags/rel_19/bench/
92 temp version. mohor 7517d 02h /dbg_interface/tags/rel_19/bench/
91 tmp version. mohor 7517d 21h /dbg_interface/tags/rel_19/bench/
90 tmp version. mohor 7518d 16h /dbg_interface/tags/rel_19/bench/
89 temp4 version. mohor 7519d 22h /dbg_interface/tags/rel_19/bench/
88 temp3 version. mohor 7520d 16h /dbg_interface/tags/rel_19/bench/
87 tmp2 version. mohor 7521d 21h /dbg_interface/tags/rel_19/bench/
80 New version of the debug interface. Not finished, yet. mohor 7534d 19h /dbg_interface/tags/rel_19/bench/
75 Simulation files. mohor 7595d 17h /dbg_interface/tags/rel_19/bench/
73 CRC logic changed. mohor 7595d 17h /dbg_interface/tags/rel_19/bench/
63 Three more chains added for cpu debug access. simons 7651d 20h /dbg_interface/tags/rel_19/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8129d 19h /dbg_interface/tags/rel_19/bench/
38 Few outputs for boundary scan chain added. mohor 8185d 19h /dbg_interface/tags/rel_19/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8189d 18h /dbg_interface/tags/rel_19/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8329d 22h /dbg_interface/tags/rel_19/bench/
15 bs_chain_o added. mohor 8331d 23h /dbg_interface/tags/rel_19/bench/
13 Signal names changed to lowercase. mohor 8333d 00h /dbg_interface/tags/rel_19/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8334d 00h /dbg_interface/tags/rel_19/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8354d 20h /dbg_interface/tags/rel_19/bench/
9 Working version. Few bugs fixed, comments added. mohor 8358d 23h /dbg_interface/tags/rel_19/bench/
6 Minor changes for simulation. mohor 8359d 22h /dbg_interface/tags/rel_19/bench/
5 Trace fixed. Some registers changed, trace simplified. mohor 8360d 19h /dbg_interface/tags/rel_19/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.