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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7461d 16h /dbg_interface/tags/rel_19/bench/
120 test stall_test added. mohor 7461d 19h /dbg_interface/tags/rel_19/bench/
117 Define name changed. mohor 7463d 15h /dbg_interface/tags/rel_19/bench/
116 Data latching changed when testing WB. mohor 7463d 16h /dbg_interface/tags/rel_19/bench/
115 More debug data added. mohor 7463d 19h /dbg_interface/tags/rel_19/bench/
114 CRC generation iand verification in bench changed. mohor 7463d 21h /dbg_interface/tags/rel_19/bench/
113 IDCODE test improved. mohor 7463d 22h /dbg_interface/tags/rel_19/bench/
112 dbg_tb_defines.v not used. mohor 7464d 16h /dbg_interface/tags/rel_19/bench/
111 Define tap_defines.v added to test bench. mohor 7464d 17h /dbg_interface/tags/rel_19/bench/
110 Waiting for "ready" improved. mohor 7464d 17h /dbg_interface/tags/rel_19/bench/
102 New version. mohor 7466d 12h /dbg_interface/tags/rel_19/bench/
101 Almost finished. mohor 7466d 13h /dbg_interface/tags/rel_19/bench/
99 cpu registers added. mohor 7467d 15h /dbg_interface/tags/rel_19/bench/
96 Working. mohor 7468d 19h /dbg_interface/tags/rel_19/bench/
95 Temp version. mohor 7469d 07h /dbg_interface/tags/rel_19/bench/
93 tmp version. mohor 7470d 18h /dbg_interface/tags/rel_19/bench/
92 temp version. mohor 7473d 22h /dbg_interface/tags/rel_19/bench/
91 tmp version. mohor 7474d 17h /dbg_interface/tags/rel_19/bench/
90 tmp version. mohor 7475d 12h /dbg_interface/tags/rel_19/bench/
89 temp4 version. mohor 7476d 18h /dbg_interface/tags/rel_19/bench/
88 temp3 version. mohor 7477d 13h /dbg_interface/tags/rel_19/bench/
87 tmp2 version. mohor 7478d 18h /dbg_interface/tags/rel_19/bench/
80 New version of the debug interface. Not finished, yet. mohor 7491d 15h /dbg_interface/tags/rel_19/bench/
75 Simulation files. mohor 7552d 13h /dbg_interface/tags/rel_19/bench/
73 CRC logic changed. mohor 7552d 14h /dbg_interface/tags/rel_19/bench/
63 Three more chains added for cpu debug access. simons 7608d 16h /dbg_interface/tags/rel_19/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8086d 15h /dbg_interface/tags/rel_19/bench/
38 Few outputs for boundary scan chain added. mohor 8142d 15h /dbg_interface/tags/rel_19/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8146d 14h /dbg_interface/tags/rel_19/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8286d 18h /dbg_interface/tags/rel_19/bench/

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