OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 104

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7478d 09h /dbg_interface/tags/rel_19/rtl/
102 New version. mohor 7478d 10h /dbg_interface/tags/rel_19/rtl/
101 Almost finished. mohor 7478d 11h /dbg_interface/tags/rel_19/rtl/
100 *** empty log message *** mohor 7479d 13h /dbg_interface/tags/rel_19/rtl/
99 cpu registers added. mohor 7479d 13h /dbg_interface/tags/rel_19/rtl/
97 Working. mohor 7480d 16h /dbg_interface/tags/rel_19/rtl/
95 Temp version. mohor 7481d 05h /dbg_interface/tags/rel_19/rtl/
94 temp version. Resets will be changed in next version. mohor 7481d 15h /dbg_interface/tags/rel_19/rtl/
93 tmp version. mohor 7482d 16h /dbg_interface/tags/rel_19/rtl/
92 temp version. mohor 7485d 20h /dbg_interface/tags/rel_19/rtl/
91 tmp version. mohor 7486d 15h /dbg_interface/tags/rel_19/rtl/
90 tmp version. mohor 7487d 10h /dbg_interface/tags/rel_19/rtl/
89 temp4 version. mohor 7488d 16h /dbg_interface/tags/rel_19/rtl/
88 temp3 version. mohor 7489d 11h /dbg_interface/tags/rel_19/rtl/
87 tmp2 version. mohor 7490d 16h /dbg_interface/tags/rel_19/rtl/
86 Tmp version. mohor 7503d 11h /dbg_interface/tags/rel_19/rtl/
83 Small fix. mohor 7503d 12h /dbg_interface/tags/rel_19/rtl/
82 New directory structure. New version of the debug interface. mohor 7503d 13h /dbg_interface/tags/rel_19/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7503d 13h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7564d 10h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7564d 12h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7566d 18h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7599d 14h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7600d 13h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7620d 14h /dbg_interface/tags/rel_19/rtl/
61 Lapsus fixed. simons 7648d 14h /dbg_interface/tags/rel_19/rtl/
59 Reset value for riscsel register set to 1. simons 7648d 14h /dbg_interface/tags/rel_19/rtl/
57 Multiple cpu support added. simons 7648d 15h /dbg_interface/tags/rel_19/rtl/
53 Trst active high. Inverted on higher layer. mohor 7915d 13h /dbg_interface/tags/rel_19/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7915d 13h /dbg_interface/tags/rel_19/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.