URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 117

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Rev	Log message	Author	Age	Path
117	Define name changed.	mohor	7499d 11h	/dbg_interface/tags/rel_19/rtl/
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7500d 18h	/dbg_interface/tags/rel_19/rtl/
106	Sensitivity list updated.	simons	7501d 16h	/dbg_interface/tags/rel_19/rtl/
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7502d 07h	/dbg_interface/tags/rel_19/rtl/
102	New version.	mohor	7502d 07h	/dbg_interface/tags/rel_19/rtl/
101	Almost finished.	mohor	7502d 08h	/dbg_interface/tags/rel_19/rtl/
100	* empty log message *	mohor	7503d 11h	/dbg_interface/tags/rel_19/rtl/
99	cpu registers added.	mohor	7503d 11h	/dbg_interface/tags/rel_19/rtl/
97	Working.	mohor	7504d 13h	/dbg_interface/tags/rel_19/rtl/
95	Temp version.	mohor	7505d 02h	/dbg_interface/tags/rel_19/rtl/
94	temp version. Resets will be changed in next version.	mohor	7505d 13h	/dbg_interface/tags/rel_19/rtl/
93	tmp version.	mohor	7506d 14h	/dbg_interface/tags/rel_19/rtl/
92	temp version.	mohor	7509d 18h	/dbg_interface/tags/rel_19/rtl/
91	tmp version.	mohor	7510d 13h	/dbg_interface/tags/rel_19/rtl/
90	tmp version.	mohor	7511d 08h	/dbg_interface/tags/rel_19/rtl/
89	temp4 version.	mohor	7512d 13h	/dbg_interface/tags/rel_19/rtl/
88	temp3 version.	mohor	7513d 08h	/dbg_interface/tags/rel_19/rtl/
87	tmp2 version.	mohor	7514d 13h	/dbg_interface/tags/rel_19/rtl/
86	Tmp version.	mohor	7527d 09h	/dbg_interface/tags/rel_19/rtl/
83	Small fix.	mohor	7527d 10h	/dbg_interface/tags/rel_19/rtl/
82	New directory structure. New version of the debug interface.	mohor	7527d 10h	/dbg_interface/tags/rel_19/rtl/
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7527d 10h	/dbg_interface/tags/rel_19/rtl/
77	MBIST chain connection fixed.	mohor	7588d 07h	/dbg_interface/tags/rel_19/rtl/
73	CRC logic changed.	mohor	7588d 09h	/dbg_interface/tags/rel_19/rtl/
71	Mbist support added.	simons	7590d 16h	/dbg_interface/tags/rel_19/rtl/
67	Lower two address lines must be always zero.	simons	7623d 11h	/dbg_interface/tags/rel_19/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7624d 11h	/dbg_interface/tags/rel_19/rtl/
63	Three more chains added for cpu debug access.	simons	7644d 12h	/dbg_interface/tags/rel_19/rtl/
61	Lapsus fixed.	simons	7672d 11h	/dbg_interface/tags/rel_19/rtl/
59	Reset value for riscsel register set to 1.	simons	7672d 12h	/dbg_interface/tags/rel_19/rtl/

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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 117

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