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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7463d 00h /dbg_interface/tags/rel_19/rtl/
119 cpu_stall_o activated as soon as bp occurs. mohor 7463d 03h /dbg_interface/tags/rel_19/rtl/
117 Define name changed. mohor 7464d 23h /dbg_interface/tags/rel_19/rtl/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7466d 06h /dbg_interface/tags/rel_19/rtl/
106 Sensitivity list updated. simons 7467d 04h /dbg_interface/tags/rel_19/rtl/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7467d 19h /dbg_interface/tags/rel_19/rtl/
102 New version. mohor 7467d 20h /dbg_interface/tags/rel_19/rtl/
101 Almost finished. mohor 7467d 21h /dbg_interface/tags/rel_19/rtl/
100 *** empty log message *** mohor 7468d 23h /dbg_interface/tags/rel_19/rtl/
99 cpu registers added. mohor 7468d 23h /dbg_interface/tags/rel_19/rtl/
97 Working. mohor 7470d 02h /dbg_interface/tags/rel_19/rtl/
95 Temp version. mohor 7470d 15h /dbg_interface/tags/rel_19/rtl/
94 temp version. Resets will be changed in next version. mohor 7471d 01h /dbg_interface/tags/rel_19/rtl/
93 tmp version. mohor 7472d 02h /dbg_interface/tags/rel_19/rtl/
92 temp version. mohor 7475d 06h /dbg_interface/tags/rel_19/rtl/
91 tmp version. mohor 7476d 01h /dbg_interface/tags/rel_19/rtl/
90 tmp version. mohor 7476d 20h /dbg_interface/tags/rel_19/rtl/
89 temp4 version. mohor 7478d 02h /dbg_interface/tags/rel_19/rtl/
88 temp3 version. mohor 7478d 20h /dbg_interface/tags/rel_19/rtl/
87 tmp2 version. mohor 7480d 01h /dbg_interface/tags/rel_19/rtl/
86 Tmp version. mohor 7492d 21h /dbg_interface/tags/rel_19/rtl/
83 Small fix. mohor 7492d 22h /dbg_interface/tags/rel_19/rtl/
82 New directory structure. New version of the debug interface. mohor 7492d 23h /dbg_interface/tags/rel_19/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7492d 23h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7553d 20h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7553d 21h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7556d 04h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7589d 00h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7589d 23h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7610d 00h /dbg_interface/tags/rel_19/rtl/

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