OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 90

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
90 tmp version. mohor 7487d 11h /dbg_interface/tags/rel_19/rtl/
89 temp4 version. mohor 7488d 17h /dbg_interface/tags/rel_19/rtl/
88 temp3 version. mohor 7489d 11h /dbg_interface/tags/rel_19/rtl/
87 tmp2 version. mohor 7490d 16h /dbg_interface/tags/rel_19/rtl/
86 Tmp version. mohor 7503d 12h /dbg_interface/tags/rel_19/rtl/
83 Small fix. mohor 7503d 13h /dbg_interface/tags/rel_19/rtl/
82 New directory structure. New version of the debug interface. mohor 7503d 13h /dbg_interface/tags/rel_19/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7503d 13h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7564d 10h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7564d 12h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7566d 19h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7599d 15h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7600d 14h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7620d 15h /dbg_interface/tags/rel_19/rtl/
61 Lapsus fixed. simons 7648d 15h /dbg_interface/tags/rel_19/rtl/
59 Reset value for riscsel register set to 1. simons 7648d 15h /dbg_interface/tags/rel_19/rtl/
57 Multiple cpu support added. simons 7648d 16h /dbg_interface/tags/rel_19/rtl/
53 Trst active high. Inverted on higher layer. mohor 7915d 14h /dbg_interface/tags/rel_19/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7915d 14h /dbg_interface/tags/rel_19/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7943d 02h /dbg_interface/tags/rel_19/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8098d 14h /dbg_interface/tags/rel_19/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8106d 20h /dbg_interface/tags/rel_19/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8113d 16h /dbg_interface/tags/rel_19/rtl/
44 Signal names changed to lower case. mohor 8113d 16h /dbg_interface/tags/rel_19/rtl/
43 Intentional error removed. mohor 8118d 15h /dbg_interface/tags/rel_19/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8118d 17h /dbg_interface/tags/rel_19/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8126d 14h /dbg_interface/tags/rel_19/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8140d 14h /dbg_interface/tags/rel_19/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8141d 15h /dbg_interface/tags/rel_19/rtl/
38 Few outputs for boundary scan chain added. mohor 8154d 14h /dbg_interface/tags/rel_19/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.