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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 94

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Rev Log message Author Age Path
94 temp version. Resets will be changed in next version. mohor 7471d 00h /dbg_interface/tags/rel_19/rtl/
93 tmp version. mohor 7472d 01h /dbg_interface/tags/rel_19/rtl/
92 temp version. mohor 7475d 05h /dbg_interface/tags/rel_19/rtl/
91 tmp version. mohor 7476d 00h /dbg_interface/tags/rel_19/rtl/
90 tmp version. mohor 7476d 19h /dbg_interface/tags/rel_19/rtl/
89 temp4 version. mohor 7478d 01h /dbg_interface/tags/rel_19/rtl/
88 temp3 version. mohor 7478d 20h /dbg_interface/tags/rel_19/rtl/
87 tmp2 version. mohor 7480d 01h /dbg_interface/tags/rel_19/rtl/
86 Tmp version. mohor 7492d 20h /dbg_interface/tags/rel_19/rtl/
83 Small fix. mohor 7492d 21h /dbg_interface/tags/rel_19/rtl/
82 New directory structure. New version of the debug interface. mohor 7492d 22h /dbg_interface/tags/rel_19/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7492d 22h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7553d 19h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7553d 21h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7556d 03h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7588d 23h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7589d 22h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7609d 23h /dbg_interface/tags/rel_19/rtl/
61 Lapsus fixed. simons 7637d 23h /dbg_interface/tags/rel_19/rtl/
59 Reset value for riscsel register set to 1. simons 7637d 23h /dbg_interface/tags/rel_19/rtl/
57 Multiple cpu support added. simons 7638d 01h /dbg_interface/tags/rel_19/rtl/
53 Trst active high. Inverted on higher layer. mohor 7904d 22h /dbg_interface/tags/rel_19/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7904d 22h /dbg_interface/tags/rel_19/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7932d 10h /dbg_interface/tags/rel_19/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8087d 22h /dbg_interface/tags/rel_19/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8096d 04h /dbg_interface/tags/rel_19/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8103d 00h /dbg_interface/tags/rel_19/rtl/
44 Signal names changed to lower case. mohor 8103d 00h /dbg_interface/tags/rel_19/rtl/
43 Intentional error removed. mohor 8108d 00h /dbg_interface/tags/rel_19/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8108d 02h /dbg_interface/tags/rel_19/rtl/

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