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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 101

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Rev Log message Author Age Path
101 Almost finished. mohor 7485d 16h /dbg_interface/tags/rel_19/rtl/verilog/
100 *** empty log message *** mohor 7486d 18h /dbg_interface/tags/rel_19/rtl/verilog/
99 cpu registers added. mohor 7486d 18h /dbg_interface/tags/rel_19/rtl/verilog/
97 Working. mohor 7487d 21h /dbg_interface/tags/rel_19/rtl/verilog/
95 Temp version. mohor 7488d 10h /dbg_interface/tags/rel_19/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7488d 21h /dbg_interface/tags/rel_19/rtl/verilog/
93 tmp version. mohor 7489d 22h /dbg_interface/tags/rel_19/rtl/verilog/
92 temp version. mohor 7493d 02h /dbg_interface/tags/rel_19/rtl/verilog/
91 tmp version. mohor 7493d 21h /dbg_interface/tags/rel_19/rtl/verilog/
90 tmp version. mohor 7494d 15h /dbg_interface/tags/rel_19/rtl/verilog/
89 temp4 version. mohor 7495d 21h /dbg_interface/tags/rel_19/rtl/verilog/
88 temp3 version. mohor 7496d 16h /dbg_interface/tags/rel_19/rtl/verilog/
87 tmp2 version. mohor 7497d 21h /dbg_interface/tags/rel_19/rtl/verilog/
86 Tmp version. mohor 7510d 17h /dbg_interface/tags/rel_19/rtl/verilog/
83 Small fix. mohor 7510d 18h /dbg_interface/tags/rel_19/rtl/verilog/
82 New directory structure. New version of the debug interface. mohor 7510d 18h /dbg_interface/tags/rel_19/rtl/verilog/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7510d 18h /dbg_interface/tags/rel_19/rtl/verilog/
77 MBIST chain connection fixed. mohor 7571d 15h /dbg_interface/tags/rel_19/rtl/verilog/
73 CRC logic changed. mohor 7571d 17h /dbg_interface/tags/rel_19/rtl/verilog/
71 Mbist support added. simons 7574d 00h /dbg_interface/tags/rel_19/rtl/verilog/
67 Lower two address lines must be always zero. simons 7606d 19h /dbg_interface/tags/rel_19/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7607d 19h /dbg_interface/tags/rel_19/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7627d 19h /dbg_interface/tags/rel_19/rtl/verilog/
61 Lapsus fixed. simons 7655d 19h /dbg_interface/tags/rel_19/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7655d 20h /dbg_interface/tags/rel_19/rtl/verilog/
57 Multiple cpu support added. simons 7655d 21h /dbg_interface/tags/rel_19/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7922d 19h /dbg_interface/tags/rel_19/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7922d 19h /dbg_interface/tags/rel_19/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7950d 07h /dbg_interface/tags/rel_19/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8105d 19h /dbg_interface/tags/rel_19/rtl/verilog/

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