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[/] [dbg_interface/] [tags/] [rel_21/] - Rev 67

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Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7591d 03h /dbg_interface/tags/rel_21/
65 WB_CNTL register added, some syncronization fixes. simons 7592d 02h /dbg_interface/tags/rel_21/
63 Three more chains added for cpu debug access. simons 7612d 03h /dbg_interface/tags/rel_21/
61 Lapsus fixed. simons 7640d 03h /dbg_interface/tags/rel_21/
59 Reset value for riscsel register set to 1. simons 7640d 03h /dbg_interface/tags/rel_21/
57 Multiple cpu support added. simons 7640d 05h /dbg_interface/tags/rel_21/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7907d 01h /dbg_interface/tags/rel_21/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7907d 01h /dbg_interface/tags/rel_21/
53 Trst active high. Inverted on higher layer. mohor 7907d 02h /dbg_interface/tags/rel_21/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7907d 02h /dbg_interface/tags/rel_21/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7934d 14h /dbg_interface/tags/rel_21/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7934d 15h /dbg_interface/tags/rel_21/
47 mon_cntl_o signals that controls monitor mux added. mohor 8090d 02h /dbg_interface/tags/rel_21/
46 Asynchronous reset used instead of synchronous. mohor 8098d 08h /dbg_interface/tags/rel_21/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8105d 04h /dbg_interface/tags/rel_21/
44 Signal names changed to lower case. mohor 8105d 04h /dbg_interface/tags/rel_21/
43 Intentional error removed. mohor 8110d 04h /dbg_interface/tags/rel_21/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8110d 06h /dbg_interface/tags/rel_21/
41 Function changed to logic because of some synthesis warnings. mohor 8118d 03h /dbg_interface/tags/rel_21/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8132d 02h /dbg_interface/tags/rel_21/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8133d 04h /dbg_interface/tags/rel_21/
38 Few outputs for boundary scan chain added. mohor 8146d 02h /dbg_interface/tags/rel_21/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8146d 06h /dbg_interface/tags/rel_21/
36 Structure changed. Hooks for jtag chain added. mohor 8150d 01h /dbg_interface/tags/rel_21/
35 Dbg support datasheet added to cvs. mohor 8174d 06h /dbg_interface/tags/rel_21/
34 Product brief added to cvs. mohor 8175d 00h /dbg_interface/tags/rel_21/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8180d 04h /dbg_interface/tags/rel_21/
32 Stupid bug that was entered by previous update fixed. mohor 8181d 03h /dbg_interface/tags/rel_21/
31 trst synchronization is not needed and was removed. mohor 8181d 04h /dbg_interface/tags/rel_21/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8192d 09h /dbg_interface/tags/rel_21/

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