OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 110

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
110 Waiting for "ready" improved. mohor 7472d 05h /dbg_interface/tags/rel_21/bench/
102 New version. mohor 7473d 23h /dbg_interface/tags/rel_21/bench/
101 Almost finished. mohor 7474d 00h /dbg_interface/tags/rel_21/bench/
99 cpu registers added. mohor 7475d 03h /dbg_interface/tags/rel_21/bench/
96 Working. mohor 7476d 07h /dbg_interface/tags/rel_21/bench/
95 Temp version. mohor 7476d 18h /dbg_interface/tags/rel_21/bench/
93 tmp version. mohor 7478d 06h /dbg_interface/tags/rel_21/bench/
92 temp version. mohor 7481d 10h /dbg_interface/tags/rel_21/bench/
91 tmp version. mohor 7482d 05h /dbg_interface/tags/rel_21/bench/
90 tmp version. mohor 7482d 23h /dbg_interface/tags/rel_21/bench/
89 temp4 version. mohor 7484d 05h /dbg_interface/tags/rel_21/bench/
88 temp3 version. mohor 7485d 00h /dbg_interface/tags/rel_21/bench/
87 tmp2 version. mohor 7486d 05h /dbg_interface/tags/rel_21/bench/
80 New version of the debug interface. Not finished, yet. mohor 7499d 03h /dbg_interface/tags/rel_21/bench/
75 Simulation files. mohor 7560d 01h /dbg_interface/tags/rel_21/bench/
73 CRC logic changed. mohor 7560d 01h /dbg_interface/tags/rel_21/bench/
63 Three more chains added for cpu debug access. simons 7616d 03h /dbg_interface/tags/rel_21/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8094d 03h /dbg_interface/tags/rel_21/bench/
38 Few outputs for boundary scan chain added. mohor 8150d 03h /dbg_interface/tags/rel_21/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8154d 02h /dbg_interface/tags/rel_21/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8294d 06h /dbg_interface/tags/rel_21/bench/
15 bs_chain_o added. mohor 8296d 07h /dbg_interface/tags/rel_21/bench/
13 Signal names changed to lowercase. mohor 8297d 07h /dbg_interface/tags/rel_21/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8298d 07h /dbg_interface/tags/rel_21/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8319d 03h /dbg_interface/tags/rel_21/bench/
9 Working version. Few bugs fixed, comments added. mohor 8323d 07h /dbg_interface/tags/rel_21/bench/
6 Minor changes for simulation. mohor 8324d 05h /dbg_interface/tags/rel_21/bench/
5 Trace fixed. Some registers changed, trace simplified. mohor 8325d 03h /dbg_interface/tags/rel_21/bench/
2 Initial official release. mohor 8330d 04h /dbg_interface/tags/rel_21/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.