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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7473d 20h /dbg_interface/tags/rel_21/bench/verilog/
120 test stall_test added. mohor 7473d 23h /dbg_interface/tags/rel_21/bench/verilog/
117 Define name changed. mohor 7475d 20h /dbg_interface/tags/rel_21/bench/verilog/
116 Data latching changed when testing WB. mohor 7475d 20h /dbg_interface/tags/rel_21/bench/verilog/
115 More debug data added. mohor 7476d 00h /dbg_interface/tags/rel_21/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7476d 01h /dbg_interface/tags/rel_21/bench/verilog/
113 IDCODE test improved. mohor 7476d 02h /dbg_interface/tags/rel_21/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7476d 21h /dbg_interface/tags/rel_21/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7476d 21h /dbg_interface/tags/rel_21/bench/verilog/
110 Waiting for "ready" improved. mohor 7476d 21h /dbg_interface/tags/rel_21/bench/verilog/
102 New version. mohor 7478d 16h /dbg_interface/tags/rel_21/bench/verilog/
101 Almost finished. mohor 7478d 17h /dbg_interface/tags/rel_21/bench/verilog/
99 cpu registers added. mohor 7479d 19h /dbg_interface/tags/rel_21/bench/verilog/
96 Working. mohor 7480d 23h /dbg_interface/tags/rel_21/bench/verilog/
95 Temp version. mohor 7481d 11h /dbg_interface/tags/rel_21/bench/verilog/
93 tmp version. mohor 7482d 23h /dbg_interface/tags/rel_21/bench/verilog/
92 temp version. mohor 7486d 02h /dbg_interface/tags/rel_21/bench/verilog/
91 tmp version. mohor 7486d 21h /dbg_interface/tags/rel_21/bench/verilog/
90 tmp version. mohor 7487d 16h /dbg_interface/tags/rel_21/bench/verilog/
89 temp4 version. mohor 7488d 22h /dbg_interface/tags/rel_21/bench/verilog/
88 temp3 version. mohor 7489d 17h /dbg_interface/tags/rel_21/bench/verilog/
87 tmp2 version. mohor 7490d 22h /dbg_interface/tags/rel_21/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7503d 20h /dbg_interface/tags/rel_21/bench/verilog/
75 Simulation files. mohor 7564d 18h /dbg_interface/tags/rel_21/bench/verilog/
73 CRC logic changed. mohor 7564d 18h /dbg_interface/tags/rel_21/bench/verilog/
63 Three more chains added for cpu debug access. simons 7620d 20h /dbg_interface/tags/rel_21/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8098d 19h /dbg_interface/tags/rel_21/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8154d 19h /dbg_interface/tags/rel_21/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8158d 19h /dbg_interface/tags/rel_21/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8298d 22h /dbg_interface/tags/rel_21/bench/verilog/

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