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[/] [dbg_interface/] [tags/] [rel_6/] - Rev 37

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37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8173d 19h /dbg_interface/tags/rel_6/
36 Structure changed. Hooks for jtag chain added. mohor 8177d 14h /dbg_interface/tags/rel_6/
35 Dbg support datasheet added to cvs. mohor 8201d 18h /dbg_interface/tags/rel_6/
34 Product brief added to cvs. mohor 8202d 12h /dbg_interface/tags/rel_6/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8207d 17h /dbg_interface/tags/rel_6/
32 Stupid bug that was entered by previous update fixed. mohor 8208d 16h /dbg_interface/tags/rel_6/
31 trst synchronization is not needed and was removed. mohor 8208d 17h /dbg_interface/tags/rel_6/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8219d 21h /dbg_interface/tags/rel_6/
29 Document revised and put tp better form. mohor 8223d 10h /dbg_interface/tags/rel_6/
28 TDO and TDO Enable signal are separated into two signals. mohor 8255d 18h /dbg_interface/tags/rel_6/
27 Warnings from synthesys tools fixed. mohor 8269d 19h /dbg_interface/tags/rel_6/
26 Warnings from synthesys tools fixed. mohor 8269d 19h /dbg_interface/tags/rel_6/
25 trst signal is synchronized to wb_clk_i. mohor 8270d 16h /dbg_interface/tags/rel_6/
24 CRC changed so more thorough testing is done. mohor 8271d 17h /dbg_interface/tags/rel_6/
23 Trace disabled by default. mohor 8277d 20h /dbg_interface/tags/rel_6/
22 Register length fixed. mohor 8277d 20h /dbg_interface/tags/rel_6/
21 CRC is returned when chain selection data is transmitted. mohor 8278d 16h /dbg_interface/tags/rel_6/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8279d 19h /dbg_interface/tags/rel_6/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8291d 19h /dbg_interface/tags/rel_6/
18 Reset signals are not combined any more. mohor 8294d 04h /dbg_interface/tags/rel_6/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8317d 18h /dbg_interface/tags/rel_6/
16 bs_chain_o port added. mohor 8319d 17h /dbg_interface/tags/rel_6/
15 bs_chain_o added. mohor 8319d 19h /dbg_interface/tags/rel_6/
14 Document updated. mohor 8320d 16h /dbg_interface/tags/rel_6/
13 Signal names changed to lowercase. mohor 8320d 19h /dbg_interface/tags/rel_6/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8321d 19h /dbg_interface/tags/rel_6/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8342d 15h /dbg_interface/tags/rel_6/
10 First official release 1.0. mohor 8346d 19h /dbg_interface/tags/rel_6/
9 Working version. Few bugs fixed, comments added. mohor 8346d 19h /dbg_interface/tags/rel_6/
8 Asynchronous set/reset not used in trace any more. mohor 8347d 17h /dbg_interface/tags/rel_6/

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