OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Three more chains added for cpu debug access. simons 7619d 04h /dbg_interface/tags/rel_6/rtl/
61 Lapsus fixed. simons 7647d 03h /dbg_interface/tags/rel_6/rtl/
59 Reset value for riscsel register set to 1. simons 7647d 04h /dbg_interface/tags/rel_6/rtl/
57 Multiple cpu support added. simons 7647d 05h /dbg_interface/tags/rel_6/rtl/
53 Trst active high. Inverted on higher layer. mohor 7914d 03h /dbg_interface/tags/rel_6/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7914d 03h /dbg_interface/tags/rel_6/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7941d 15h /dbg_interface/tags/rel_6/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8097d 03h /dbg_interface/tags/rel_6/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8105d 09h /dbg_interface/tags/rel_6/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8112d 05h /dbg_interface/tags/rel_6/rtl/
44 Signal names changed to lower case. mohor 8112d 05h /dbg_interface/tags/rel_6/rtl/
43 Intentional error removed. mohor 8117d 04h /dbg_interface/tags/rel_6/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8117d 06h /dbg_interface/tags/rel_6/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8125d 03h /dbg_interface/tags/rel_6/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8139d 03h /dbg_interface/tags/rel_6/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8140d 04h /dbg_interface/tags/rel_6/rtl/
38 Few outputs for boundary scan chain added. mohor 8153d 03h /dbg_interface/tags/rel_6/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8153d 07h /dbg_interface/tags/rel_6/rtl/
36 Structure changed. Hooks for jtag chain added. mohor 8157d 02h /dbg_interface/tags/rel_6/rtl/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8187d 05h /dbg_interface/tags/rel_6/rtl/
32 Stupid bug that was entered by previous update fixed. mohor 8188d 04h /dbg_interface/tags/rel_6/rtl/
31 trst synchronization is not needed and was removed. mohor 8188d 05h /dbg_interface/tags/rel_6/rtl/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8199d 10h /dbg_interface/tags/rel_6/rtl/
28 TDO and TDO Enable signal are separated into two signals. mohor 8235d 06h /dbg_interface/tags/rel_6/rtl/
27 Warnings from synthesys tools fixed. mohor 8249d 07h /dbg_interface/tags/rel_6/rtl/
26 Warnings from synthesys tools fixed. mohor 8249d 07h /dbg_interface/tags/rel_6/rtl/
25 trst signal is synchronized to wb_clk_i. mohor 8250d 04h /dbg_interface/tags/rel_6/rtl/
23 Trace disabled by default. mohor 8257d 08h /dbg_interface/tags/rel_6/rtl/
22 Register length fixed. mohor 8257d 08h /dbg_interface/tags/rel_6/rtl/
21 CRC is returned when chain selection data is transmitted. mohor 8258d 04h /dbg_interface/tags/rel_6/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.