OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7981d 07h /dbg_interface/tags/rel_6/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8136d 19h /dbg_interface/tags/rel_6/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8145d 01h /dbg_interface/tags/rel_6/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8151d 21h /dbg_interface/tags/rel_6/rtl/verilog/
44 Signal names changed to lower case. mohor 8151d 21h /dbg_interface/tags/rel_6/rtl/verilog/
43 Intentional error removed. mohor 8156d 20h /dbg_interface/tags/rel_6/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8156d 22h /dbg_interface/tags/rel_6/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8164d 19h /dbg_interface/tags/rel_6/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8178d 19h /dbg_interface/tags/rel_6/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8179d 20h /dbg_interface/tags/rel_6/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8192d 19h /dbg_interface/tags/rel_6/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8192d 23h /dbg_interface/tags/rel_6/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8196d 18h /dbg_interface/tags/rel_6/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8226d 21h /dbg_interface/tags/rel_6/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8227d 20h /dbg_interface/tags/rel_6/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8227d 21h /dbg_interface/tags/rel_6/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8239d 02h /dbg_interface/tags/rel_6/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8274d 22h /dbg_interface/tags/rel_6/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8289d 00h /dbg_interface/tags/rel_6/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8289d 00h /dbg_interface/tags/rel_6/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8289d 20h /dbg_interface/tags/rel_6/rtl/verilog/
23 Trace disabled by default. mohor 8297d 00h /dbg_interface/tags/rel_6/rtl/verilog/
22 Register length fixed. mohor 8297d 00h /dbg_interface/tags/rel_6/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8297d 20h /dbg_interface/tags/rel_6/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8298d 23h /dbg_interface/tags/rel_6/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8310d 23h /dbg_interface/tags/rel_6/rtl/verilog/
18 Reset signals are not combined any more. mohor 8313d 08h /dbg_interface/tags/rel_6/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8336d 22h /dbg_interface/tags/rel_6/rtl/verilog/
15 bs_chain_o added. mohor 8338d 23h /dbg_interface/tags/rel_6/rtl/verilog/
13 Signal names changed to lowercase. mohor 8339d 23h /dbg_interface/tags/rel_6/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.