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[/] [dbg_interface/] [tags/] [rel_8/] - Rev 39

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Rev Log message Author Age Path
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8128d 06h /dbg_interface/tags/rel_8/
38 Few outputs for boundary scan chain added. mohor 8141d 05h /dbg_interface/tags/rel_8/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8141d 09h /dbg_interface/tags/rel_8/
36 Structure changed. Hooks for jtag chain added. mohor 8145d 04h /dbg_interface/tags/rel_8/
35 Dbg support datasheet added to cvs. mohor 8169d 09h /dbg_interface/tags/rel_8/
34 Product brief added to cvs. mohor 8170d 02h /dbg_interface/tags/rel_8/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8175d 07h /dbg_interface/tags/rel_8/
32 Stupid bug that was entered by previous update fixed. mohor 8176d 06h /dbg_interface/tags/rel_8/
31 trst synchronization is not needed and was removed. mohor 8176d 07h /dbg_interface/tags/rel_8/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8187d 11h /dbg_interface/tags/rel_8/
29 Document revised and put tp better form. mohor 8191d 00h /dbg_interface/tags/rel_8/
28 TDO and TDO Enable signal are separated into two signals. mohor 8223d 08h /dbg_interface/tags/rel_8/
27 Warnings from synthesys tools fixed. mohor 8237d 09h /dbg_interface/tags/rel_8/
26 Warnings from synthesys tools fixed. mohor 8237d 09h /dbg_interface/tags/rel_8/
25 trst signal is synchronized to wb_clk_i. mohor 8238d 06h /dbg_interface/tags/rel_8/
24 CRC changed so more thorough testing is done. mohor 8239d 07h /dbg_interface/tags/rel_8/
23 Trace disabled by default. mohor 8245d 10h /dbg_interface/tags/rel_8/
22 Register length fixed. mohor 8245d 10h /dbg_interface/tags/rel_8/
21 CRC is returned when chain selection data is transmitted. mohor 8246d 06h /dbg_interface/tags/rel_8/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8247d 09h /dbg_interface/tags/rel_8/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8259d 09h /dbg_interface/tags/rel_8/
18 Reset signals are not combined any more. mohor 8261d 18h /dbg_interface/tags/rel_8/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8285d 08h /dbg_interface/tags/rel_8/
16 bs_chain_o port added. mohor 8287d 07h /dbg_interface/tags/rel_8/
15 bs_chain_o added. mohor 8287d 09h /dbg_interface/tags/rel_8/
14 Document updated. mohor 8288d 06h /dbg_interface/tags/rel_8/
13 Signal names changed to lowercase. mohor 8288d 09h /dbg_interface/tags/rel_8/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8289d 09h /dbg_interface/tags/rel_8/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8310d 05h /dbg_interface/tags/rel_8/
10 First official release 1.0. mohor 8314d 09h /dbg_interface/tags/rel_8/

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