OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_8/] - Rev 41

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
41 Function changed to logic because of some synthesis warnings. mohor 8122d 00h /dbg_interface/tags/rel_8/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8136d 00h /dbg_interface/tags/rel_8/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8137d 01h /dbg_interface/tags/rel_8/
38 Few outputs for boundary scan chain added. mohor 8150d 00h /dbg_interface/tags/rel_8/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8150d 04h /dbg_interface/tags/rel_8/
36 Structure changed. Hooks for jtag chain added. mohor 8153d 23h /dbg_interface/tags/rel_8/
35 Dbg support datasheet added to cvs. mohor 8178d 04h /dbg_interface/tags/rel_8/
34 Product brief added to cvs. mohor 8178d 21h /dbg_interface/tags/rel_8/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8184d 02h /dbg_interface/tags/rel_8/
32 Stupid bug that was entered by previous update fixed. mohor 8185d 01h /dbg_interface/tags/rel_8/
31 trst synchronization is not needed and was removed. mohor 8185d 02h /dbg_interface/tags/rel_8/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8196d 06h /dbg_interface/tags/rel_8/
29 Document revised and put tp better form. mohor 8199d 19h /dbg_interface/tags/rel_8/
28 TDO and TDO Enable signal are separated into two signals. mohor 8232d 03h /dbg_interface/tags/rel_8/
27 Warnings from synthesys tools fixed. mohor 8246d 04h /dbg_interface/tags/rel_8/
26 Warnings from synthesys tools fixed. mohor 8246d 04h /dbg_interface/tags/rel_8/
25 trst signal is synchronized to wb_clk_i. mohor 8247d 01h /dbg_interface/tags/rel_8/
24 CRC changed so more thorough testing is done. mohor 8248d 02h /dbg_interface/tags/rel_8/
23 Trace disabled by default. mohor 8254d 05h /dbg_interface/tags/rel_8/
22 Register length fixed. mohor 8254d 05h /dbg_interface/tags/rel_8/
21 CRC is returned when chain selection data is transmitted. mohor 8255d 01h /dbg_interface/tags/rel_8/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8256d 04h /dbg_interface/tags/rel_8/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8268d 04h /dbg_interface/tags/rel_8/
18 Reset signals are not combined any more. mohor 8270d 13h /dbg_interface/tags/rel_8/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8294d 03h /dbg_interface/tags/rel_8/
16 bs_chain_o port added. mohor 8296d 02h /dbg_interface/tags/rel_8/
15 bs_chain_o added. mohor 8296d 04h /dbg_interface/tags/rel_8/
14 Document updated. mohor 8297d 01h /dbg_interface/tags/rel_8/
13 Signal names changed to lowercase. mohor 8297d 04h /dbg_interface/tags/rel_8/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8298d 04h /dbg_interface/tags/rel_8/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.