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[/] [dbg_interface/] [tags/] [rev_23/] - Rev 91

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Rev Log message Author Age Path
91 tmp version. mohor 7485d 10h /dbg_interface/tags/rev_23/
90 tmp version. mohor 7486d 05h /dbg_interface/tags/rev_23/
89 temp4 version. mohor 7487d 11h /dbg_interface/tags/rev_23/
88 temp3 version. mohor 7488d 05h /dbg_interface/tags/rev_23/
87 tmp2 version. mohor 7489d 10h /dbg_interface/tags/rev_23/
86 Tmp version. mohor 7502d 06h /dbg_interface/tags/rev_23/
85 New directory structure. New debug interface. mohor 7502d 07h /dbg_interface/tags/rev_23/
84 Removed files that are not needed any more. mohor 7502d 07h /dbg_interface/tags/rev_23/
83 Small fix. mohor 7502d 07h /dbg_interface/tags/rev_23/
82 New directory structure. New version of the debug interface. mohor 7502d 08h /dbg_interface/tags/rev_23/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7502d 08h /dbg_interface/tags/rev_23/
80 New version of the debug interface. Not finished, yet. mohor 7502d 08h /dbg_interface/tags/rev_23/
77 MBIST chain connection fixed. mohor 7563d 05h /dbg_interface/tags/rev_23/
75 Simulation files. mohor 7563d 06h /dbg_interface/tags/rev_23/
74 Removed. mohor 7563d 06h /dbg_interface/tags/rev_23/
73 CRC logic changed. mohor 7563d 06h /dbg_interface/tags/rev_23/
71 Mbist support added. simons 7565d 13h /dbg_interface/tags/rev_23/
70 A pdf copy of existing doc document. simons 7572d 15h /dbg_interface/tags/rev_23/
69 WBCNTL added, multiple CPU support described. simons 7593d 04h /dbg_interface/tags/rev_23/
67 Lower two address lines must be always zero. simons 7598d 09h /dbg_interface/tags/rev_23/
65 WB_CNTL register added, some syncronization fixes. simons 7599d 08h /dbg_interface/tags/rev_23/
63 Three more chains added for cpu debug access. simons 7619d 09h /dbg_interface/tags/rev_23/
61 Lapsus fixed. simons 7647d 09h /dbg_interface/tags/rev_23/
59 Reset value for riscsel register set to 1. simons 7647d 09h /dbg_interface/tags/rev_23/
57 Multiple cpu support added. simons 7647d 10h /dbg_interface/tags/rev_23/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7914d 07h /dbg_interface/tags/rev_23/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7914d 07h /dbg_interface/tags/rev_23/
53 Trst active high. Inverted on higher layer. mohor 7914d 08h /dbg_interface/tags/rev_23/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7914d 08h /dbg_interface/tags/rev_23/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7941d 20h /dbg_interface/tags/rev_23/

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