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[/] [dbg_interface/] [tags/] [sdram_test_working/] - Rev 35

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Rev Log message Author Age Path
35 Dbg support datasheet added to cvs. mohor 8181d 11h /dbg_interface/tags/sdram_test_working/
34 Product brief added to cvs. mohor 8182d 05h /dbg_interface/tags/sdram_test_working/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8187d 10h /dbg_interface/tags/sdram_test_working/
32 Stupid bug that was entered by previous update fixed. mohor 8188d 08h /dbg_interface/tags/sdram_test_working/
31 trst synchronization is not needed and was removed. mohor 8188d 09h /dbg_interface/tags/sdram_test_working/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8199d 14h /dbg_interface/tags/sdram_test_working/
29 Document revised and put tp better form. mohor 8203d 03h /dbg_interface/tags/sdram_test_working/
28 TDO and TDO Enable signal are separated into two signals. mohor 8235d 11h /dbg_interface/tags/sdram_test_working/
27 Warnings from synthesys tools fixed. mohor 8249d 12h /dbg_interface/tags/sdram_test_working/
26 Warnings from synthesys tools fixed. mohor 8249d 12h /dbg_interface/tags/sdram_test_working/
25 trst signal is synchronized to wb_clk_i. mohor 8250d 08h /dbg_interface/tags/sdram_test_working/
24 CRC changed so more thorough testing is done. mohor 8251d 10h /dbg_interface/tags/sdram_test_working/
23 Trace disabled by default. mohor 8257d 12h /dbg_interface/tags/sdram_test_working/
22 Register length fixed. mohor 8257d 12h /dbg_interface/tags/sdram_test_working/
21 CRC is returned when chain selection data is transmitted. mohor 8258d 08h /dbg_interface/tags/sdram_test_working/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8259d 11h /dbg_interface/tags/sdram_test_working/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8271d 12h /dbg_interface/tags/sdram_test_working/
18 Reset signals are not combined any more. mohor 8273d 21h /dbg_interface/tags/sdram_test_working/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8297d 10h /dbg_interface/tags/sdram_test_working/
16 bs_chain_o port added. mohor 8299d 10h /dbg_interface/tags/sdram_test_working/
15 bs_chain_o added. mohor 8299d 11h /dbg_interface/tags/sdram_test_working/
14 Document updated. mohor 8300d 09h /dbg_interface/tags/sdram_test_working/
13 Signal names changed to lowercase. mohor 8300d 12h /dbg_interface/tags/sdram_test_working/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8301d 12h /dbg_interface/tags/sdram_test_working/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8322d 08h /dbg_interface/tags/sdram_test_working/
10 First official release 1.0. mohor 8326d 12h /dbg_interface/tags/sdram_test_working/
9 Working version. Few bugs fixed, comments added. mohor 8326d 12h /dbg_interface/tags/sdram_test_working/
8 Asynchronous set/reset not used in trace any more. mohor 8327d 10h /dbg_interface/tags/sdram_test_working/
7 First official release 1.0. mohor 8327d 10h /dbg_interface/tags/sdram_test_working/
6 Minor changes for simulation. mohor 8327d 10h /dbg_interface/tags/sdram_test_working/

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